L9803 datasheet(30/126 Pages) STMICROELECTRONICS

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Clocks, Reset, Interrupts & Power saving modes

L9803

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3.7.4

Halt Mode

The Halt mode is the MCU lowest power consumption mode. The Halt mode is entered by

executing the HALT instruction. The internal oscillator is then turned off, causing all internal

processing to be stopped, including the operation of the on-chip peripherals.

When entering Halt mode, the I bit in the CC Register is cleared so as to enable External

Interrupts. If an interrupt occurs, the CPU becomes active.

The MCU can exit the Halt mode upon reception of either an external interrupt (I0), a

internal interrupt coming from the CAN peripheral (I1) or a reset. The oscillator is then

turned on and a stabilisation time is provided before releasing CPU operation. The

stabilisation time is 4096 CPU clock cycles.

After the start up delay, the CPU continues operation by servicing the interrupt which wakes

it up or by fetching the reset vector if a reset wakes it up.

Note:

The Halt mode cannot be used when the watchdog or the Safeguard are enabled, if the

HALT instruction is executed while the watchdog or safeguard system are enabled, a reset is

automatically generated thus resetting the entire MCU.

Halt Mode affects only the digital section of the device. All the analog circuit remain in their

status, including ADC, voltage regulators, bus transceivers and power bridge.

Figure 14.

Halt Mode Flow Chart

EXTERNAL

INTERRUPT

RESET

HALT INSTRUCTION

4096 CPU CLOCK

FETCH RESET VECTOR

OR SERVICE INTERRUPT

CYCLES DELAY

CPU CLOCK

OSCILLATOR

PERIPH. CLOCK

I-BIT

SET

CPU CLOCK

OSCILLATOR

PERIPH. CLOCK

I-BIT

OFF

CLEARED

OFF

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