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Datasheet

Electrical Specifications

2.8

Test Access Port (TAP) Connection

Due to the voltage levels supported by other components in the Test Access Port (TAP) logic, it is

recommended that the Pentium 4 processor in the 775-land package be first in the TAP chain and

followed by any other components within the system. A translation buffer should be used to

connect to the rest of the chain unless one of the other components is capable of accepting an input

of the appropriate voltage level. Similar considerations must be made for TCK, TMS, TRST#, TDI,

and TDO. Two copies of each signal may be required, with each driving a different voltage level.

2.9

FSB Frequency Select Signals (BSEL[2:0])

The BSEL[2:0] signals are used to select the frequency of the processor input clock (BCLK[1:0]).

Table 2-6 defines the possible combinations of the signals and the frequency associated with each

combination. The required frequency is determined by the processor, chipset, and clock

synthesizer. All agents must operate at the same frequency.

The Pentium 4 processor in the 775-land package currently operates at a 533 MHz or 800 MHz

FSB frequency (selected by a 133 MHz or 200 MHz BCLK[1:0] frequency). Individual processors

will only operate at their specified FSB frequency.

For more information about these signals, refer to Section 4.2.

Table 2-6. BSEL[2:0] Frequency Table for BCLK[1:0]

BSEL2

BSEL1

BSEL0

FSB Frequency

RESERVED

133 MHz

RESERVED

200 MHz

RESERVED

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