TDA8023 datasheet(21/32 Pages) NXP

21 / 32 page

TDA8023_1

Product data sheet

Rev. 01 — 16 July 2007

21 of 32

NXP Semiconductors

TDA8023

Low power IC card interface

rise time

input; from VIL(max) to VIH(min)

µs

tTLH

clock rise time

output transition time; from

10 % to 90 % of VDD(INTF);

CL <30pF

0.1

µs

Rpu(int)

internal pull-up resistance

between pin I/OUC and pin

VDDI

[1] 11

Ω

Clock input: pin CLKIN

fCLKIN

frequency on pin CLKIN

MHz

VIL

LOW-level input voltage

VDD(INTF) > 2 V

0.3VDD(INTF)

1.5 V < VDD(INTF) < 2 V

0.15VDD(INTF)

VIH

HIGH-level input voltage

VDD(INTF) > 2 V

0.7VDD(INTF)

-VDD(INTF) + 0.3

1.5 V < VDD(INTF) < 2 V

0.85VDD(INTF) -VDD(INTF) + 0.3

rise time

0.1 / fCLKIN

fall time

0.1 / fCLKIN

Logic inputs: pins SAD0, SPRES and SDWN

VIL

LOW-level input voltage

−0.3

0.3VDD(INTF)

VIH

HIGH-level input voltage

0.7VDD

-VDD(INTF) + 0.3

ILIL

LOW-level input leakage

current

±1

µA

ILIH

HIGH-level input leakage

current

±1

µA

input capacitance

Interrupt line: pin INT; open-drain active-LOW output

VOL

LOW-level output voltage

Io = 2 mA

0.3

ILH

HIGH-level leakage current

µA

Serial data input/output: pin SDA; open-drain

VIL

LOW-level input voltage

−0.3

0.3VDD

VIH

HIGH-level input voltage

0.7VDD

6.5

VOL1

LOW-level output voltage

IOL = 3 mA

0.3

ILH

HIGH-level leakage current

input or output

µA

ILL

LOW-level leakage current

depends on the pull-up

resistance; input or output

µA

Serial clock input: pin SCL

VIL

LOW-level input voltage

−0.3

0.3VDD

VIH

HIGH-level input voltage

0.7VDD

6.5

ILIH

HIGH-level input leakage

current

µA

IIL

LOW-level input current

depends on the pull-up

resistance

µA

Table 20.

Interface signals to host controller …continued

VDD = 3.3 V; VDD(INTF) = 1.5 V; fCLKIN = 10 MHz; GND = 0 V; Tamb = 25 °C; unless otherwise speciﬁed.

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

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