FS8170

Page 12

July 2005

Measurement Circuit Setup

The circuit shown in Fig. 4 is used for measuring the input sensitivity of the FIN input of

the PLL.

Fig. 4 – FIN input sensitivity test circuit

9

10

11

12

13

14

15

16

8

7

6

5

4

3

2

1

XIN

XOUT

VP

VCC

DO

VSS

XFIN

FIN

φP

FOLD

ZC

EN

LE

DATA

CLK

φR

S.G.

S.G.

1000pF

1000pF

50

Ω

50

Ω

1000pF

0.1

µF

From Controller

Vcc

To Counter