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KM418RD8ACD-RK80 Folha de dados(PDF) 52 Page - Samsung semiconductor

Nome de Peças KM418RD8ACD-RK80
Descrição Electrónicos  128/144Mbit RDRAM 256K x 16/18 bit x 2*16 Dependent Banks Direct RDRAMTM
PDF  64 Pages
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Fabricante Electrônico  SAMSUNG [Samsung semiconductor]
Página de início  http://www.samsung.com/Products/Semiconductor
Logo SAMSUNG - Samsung semiconductor

KM418RD8ACD-RK80 Folha de dados(HTML) 52 Page - Samsung semiconductor

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Page 49
KM416RD8AC(D)/KM418RD8AC(D)
Direct RDRAM™
Rev. 1.01 Oct. 1999
RSL - Transmit Timing
Figure 55 is a timing diagram which shows the detailed
requirements for the RSL output signals on the Channel.
The DQA and DQB signals are outputs to transmit informa-
tion that is received by a Direct RAC on the Channel. Each
signal is driven twice per tCYCLE interval. The beginning
and end of the even transmit window is at the 75% point of
the previous cycle and at the 25% point of the current cycle.
The beginning and end of the odd transmit window is at the
25% point and at the 75% point of the current cycle. These
transmit points are measured relative to the crossing points
of the falling CTM clock edge. The size of the actual
transmit window is less than the ideal tCYCLE/2, as indicated
by the non-zero values of tQ,MIN and tQ,MAX. The tQ param-
eters are measured at the 50% voltage point of the output
transition.
The tQR and tQF rise- and fall-time parameters are measured
at the 20% and 80% points of the output transition.
Figure 55: RSL Timing - Data Signals for Transmit
tQ,MIN
tQ,MAX
tQ,MAX
tQ,MIN
0.25•t CYCLE
VQH
50%
VQL
80%
20%
VCIH
50%
VCIL
80%
20%
CTM
CTMN
tQF
tQR
even
odd
0.75•t CYCLE
0.75•t CYCLE
DQA
DQB
VCM
VX+
VX-



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