SAN3010

sames

sames

sames

sames

2/13

SAN3010 Application Note (this document):

AN3010 Schematic:

Rev.: A02

AN3010 Sample Software

Rev.: A01

The interface must be capable of forcing the keyboard rows (hereafter indicated as R1...R4) both low (Vss) and

is forced at the same time while the remaining rows/columns must be high ohmic (hereafter indicated as Hi Z).

Since only one row/column must be driven at the same time, a decoder (IC5 = 74138) was implemented to save

pin count of the µC. 3 output ports were used for row/column selection, 1 output port to disable all rows/columns

and 1 output port for the 3-state buffer inputs to select forcing high or low .

One µC pin must be configured as input for handshake.

If 9 output + 1 input pins are available from the µC (8 row/column selectors, 1 force hi/lo selector , 1 handshake

input) , IC5 = 74138 can be omitted.

IC3 & 4 (=74HC125) are separately addressable 3-state buffers.

A simple discrete NOR gate (Q1,D2,D3,R9..11) is used for synchronization.

The SA253x Single Chip Telephone can be connected to a µC for key entry when the following conditions are met:

If the µC is supplied with >4V a current limiter (serial resistor) must be added to the row/column pins of the

SA253x.

Row driver : 4 Tristate output pins, each separately adjustable as either output (Hi/Lo) or tristate . Only one row is

driven at the same time, all other rows/columns are high ohmic.

Column driver: Tristate output pins, each separately adjustable as either output (Hi) or tristate. Only one column is

driven at the same time, all other rows/columns are high ohmic.

Synchronization: The SA253x is intentionally designed for low standby power, so no oscillator is running as long as

no key is pressed. All the external row/column driving is done asynchronously. The scanning sequence is

synchronized by triggering a rising edge on specific columns (see table 1).

Therefore a 1-bit input must be provided for the synchronization.

See also: Appendix A:

One solution which only requires 5 output pins and 1 input pin is shown in the attached schematic. A common µC

(80C51-family) is used. This controller is widely known, so both hardware and software description in this

application note should be easily understood which simplifies adaption to any other controller.

The rows/columns are driven by 8 separately selectable tristate buffers (e.g. 74HC125). Power supply is 5V,

therefore resistors R2...R8 are necessary to provide adaption to the 4V-logic of the SA253x.

R1 is always connected by a 5kOhms resistor to prevent collision of two outputs when it initiates the key entry in an

unsynchronous state.

4 Revision status

5 General Description

6 Hardware configuration

7 Application schematic: