538

Motor driver ICs

BA6477FS

FCircuit operation

(1)

Motor drive circuit

The motor driver is based on a 3-phase, full-wave soft

switching, current drive system in which the position of

rotor is sensed by Hall elements. The total drive current

through a voltage comparison. The IC consists of Hall

amplifiers, an amplitude control circuit, a driver, an error

amplifier, and a current feedback amplifier (Fig. 1).

The waveforms of different steps along the signal path

from the Hall elements to the motor driver output are

shown in Fig. 2. The Hall amplifiers receive the Hall ele-

ments voltage signals as differential signals. Next, by de-

ducting the voltage signal of Hall elements 2 from the

voltage signal of Hall elements 1, current signal H1,

which has a phase 30 degrees ahead of Hall elements 1,

is created. Current signals H2 and H3 are created like-

wise. The amplitude control circuit then amplifies the H1,

H2, and H3 signal according to the current feedback am-

plifier signal. Then, drive current signals are produced at

A1, A2, and A3 by applying a constant magnification fac-

tor. Because a soft switching system is employed, the

drive current has low noise and a low total current ripple.

The total drive current is controlled by the error amplifier

input voltage. The error amplifier has a voltage gain of

about –11dB (a factor of 0.28). The current feedback am-

plifier regulates the total drive current, so that the error

which has been voltage-converted from the total drive

iter voltage (Vcl), the constant voltage Vcl takes prece-

dence, and a current limit is applied at the level of

The current feedback amplifier tends to oscillate be-

cause it receives all the feedback with a gain of 0dB. To

prevent this oscillation, connect an external capacitor to

high frequency gain.

(2)

Speed control circuit

The speed control circuit is a non-adjustable digital servo

system that uses a frequency locked loop (FLL). The cir-

cuit consists of an 1 / 2 frequency divider, an FG amplifier,

and a speed discriminator (Fig. 3).

An internal reference is generated from an external clock

signal input. The 1 / 2 frequency divider reduces the fre-

quency of the OSC signal. The FG amplifier amplifies the

minute voltage generated by the motor FG pattern and

produces a rectangular-shaped speed signal. The FG

internal resistance ratio.

For noise filtering, a high-pass filter is given by C3 and a

resistor of 1.6k

Ω (typical), and a low-pass filter is given

by C4 and a resistor of 200k

Ω (typical). The cutoff fre-

spectively) are given by:

The C3 and C4 capacitances should be set so as to satis-

fy the following relationship:

inputs have a hysteresis.

The speed discriminator divides the reference clock and

compares with the reference frequency, and then outputs

an error pulse according to the frequency difference. The

motor rotational speed N is given in the following formula.

n is (speed discriminator count)

2,

z is the FG tooth number.

The discriminator count depends on the speed control

pin voltage.

The integrator flattens out the error pulse of the speed

discriminator and creates a control signal for the motor

drive circuit (Fig. 4).

(3)

Index amplifier

The index amplifier is a hysteresis amplifier with a typical

hysteresis width of +18mV and –22mV. The input pin is

not biased internally.

1

2

π

1.6k

Ω C3

1

2

π

200k

Ω

C4

(1)

n

S

1

z