7 / 12 page
2-173
RF2153
Rev A18 001114
2
Application Schematic
US - TDMA
100
Ω
1 nH
15 pF
10 nF
15 pF
15 pF
RF IN
1
2
3
4
5
13
12
11
10
9
678
16
14
15
15 pF
4.7 k
Ω
15 pF
VREG
VMODE
15 nH
4.7 pF**
1.8 pF**
15 pF
RF OUT
12 nH*
15 pF
10 nF
1 pF
TL
1
TL
2
10 pF
10 nF
V
CC
TL
3
TDMA (US)
Transmission
Line Length
TL
1
20 mils
160 mils
10 mils
TL
2
TL
3
Tied together for optimum linearity
* High Q inductor (i.e., Coilcraft 0805HQ-series).
**High Q capacitors (i.e., Johanson C-series).
0
Ω
0
Ω
Bypassing for V
CC
2nd Interstage tuning for
centering frequency response
1st Interstage tuning to
match input return loss
To match input return loss
and vary gain
Ground for 2nd
Harmonic Trap
Bias return
Bypassing for
V
REG1 and VREG2
Matching Network for
optimum load impedance
Portuguese ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
