FS401LF datasheet(87/104 Pages) ETC2

87 / 104 page

FS401, FS403

PRODUCT SPECIFICATION

REV. NO. 1.7

JANUARY 24, 2007

Figure 18. 7-bit Slave Address with Read/Write\ Bit

R/W

ACK0

SDA

SCL

Figure 19. 10-bit address transfer, upper two bits

ACK1

ACK0

SDA

SCL

Figure 20. 10-bit address transfer, lower eight bits

There are five steps within a serial bus cycle:

1. Start signal

2. Slave address byte

3. Pointer register address byte

4. Data byte to read or write

5. Stop signal

When the serial interface is inactive (SIOCLK = H and SIODATA = H) communications are initiated by

sending a start signal. The start signal (Figure 16, left waveform) is a HIGH-to-LOW transition on

SIODATA while SIOCLK is HIGH. This signal alerts all slaved devices that a data transfer sequence is

imminent.

For 7-bit addressing, the first eight bits of data transferred after a start signal comprise a seven bit slave

address and a single R/W bit (Read = H, Write = L). As shown in Figure 17, the R/W bit indicates the

direction of data transfer, read from or write to the slave device. If the transmitted slave address matches

the address of the FS400 (set by the state of the SIOA0 and SIOA10/7 input pins in Table 5. Serial Port

Addresses, the FS400 acknowledges by bringing SIODATA LOW on the 9th SIOCLK pulse (see Figure

18). If the addresses do not match, the FS400 does not acknowledge.

With 10-bit addressing (see Figure 19 and Figure 20), data is still transferred in 8-bit chunks. The upper

two bits of the ten bit address are transferred as the lower two bits of the first byte along with the reserved

sequence 11110 in the upper five bits and the R/W bit. The lower eight bits are transferred in the second

byte without a R/W bit. Subsequent data reads or writes follow the 7-bit transfer sequences.

For each byte of data read or written, the MSB is the first bit of the sequence.

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