MAC7200 datasheet(41/976 Pages) FREESCALE

41 / 976 page

MAC7200 Microcontroller Family Reference Manual, Rev. 2

Freescale Semiconductor

xli

Figures

1-1

Orderable Part Number Example.............................................................................................8

1-2

MAC72xx Architecture Overview.........................................................................................13

4-1

PAC7211/PAC7212 Pin Assignment, 144 QFP ....................................................................30

4-2

PAC7201/PAC7202 Pin Assignment, 144 QFP ....................................................................31

4-3

MAC7241/MAC7242 Pin assignments, 100 Pin LQFP package .........................................32

4-4

Bidirectional Open Drain Pin.................................................................................................39

4-5

PLL Loop Filter Connections ................................................................................................39

5-1

MAC72xx Clock Tree............................................................................................................60

5-2

CRG Generated Clocks..........................................................................................................62

5-3

Timing of CRG Generated Clocks.........................................................................................63

5-4

ALC 1:1 Mode Clock Path ....................................................................................................64

5-5

ALC PLL Mode Clock Path ..................................................................................................65

5-6

External Clock 1:1 Mode Clock Path ....................................................................................66

5-7

External Clock PLL Mode Clock Path ..................................................................................67

5-8

System Clock Gating .............................................................................................................70

6-1

MAC72xx Resets ...................................................................................................................72

8-1

JTAG Interface Overview......................................................................................................92

8-2

JTAG TCK Routing ...............................................................................................................93

8-3

JTAG TMS Routing...............................................................................................................93

8-4

JTAG TDI Routing ................................................................................................................94

8-5

JTAG TDO Routing...............................................................................................................94

8-6

JTAG Synchronization Circuit ..............................................................................................95

8-7

JTAG Synchronization Timing (TCK = 1/3 frequency of ipg_clk) ......................................96

8-8

JTAG Synchronization Timing (TCK = 1/8 frequency of ipg_clk) ......................................96

8-9

Halt Mode Overview..............................................................................................................98

8-10

Monitor Mode Overview .......................................................................................................99

9-1

MAC72xx Memory Map Overview.....................................................................................103

9-2

MAC72x1 Memory Map Example .....................................................................................104

9-3

MAC72x2 Memory Map Example ....................................................................................105

9-4

Device Programming Sequence ...........................................................................................124

9-5

Device “Normal” Boot Sequence ........................................................................................124

11-1

A7S Nexus3 Functional Block Diagram..............................................................................129

11-2

Single Pin MSEO Transfers.................................................................................................145

11-3

Two Pin MSEO Transfers....................................................................................................146

11-4

JTAG ID Register ................................................................................................................149

11-5

Client Select Control Register (CSC) ..................................................................................151

Figure

Number

Title

Page

Number

MAC7200 Folha de dados(PDF) 41 Page - Freescale Semiconductor, Inc

MAC7200 Folha de dados(HTML) 41 Page - Freescale Semiconductor, Inc

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Folha de dados Download

Ligação URL