ADT7490ARQZ-R7 datasheet(5/75 Pages) ONSEMI

5 / 75 page

ADT7490

http://onsemi.com

ELECTRICAL CHARACTERISTICS TA = TMIN to TMAX, VCC = VMIN to VMAX, unless otherwise noted. (Note 1)

Parameter

Unit

Max

Typ

Min

Conditions

Digital I/O (PECI Pin) (Note 2)

VTT, Supply Voltage

0.95

1.26

Input High Voltage , VIH

0.55 x VTT

(Note 3)

Input Low Voltage, VIL

0.5 x VTT

(Note 3)

Hysteresis (Note 2)

Hysteresis between input switching

levels

0.1 x VTT

(Note 3)

High Level Output Source Current,

ISOURCE

VOH = 0.75 x VTT

6.0

Low Level Output Sink Current, ISINK

VOL = 0.25 x VTT

0.5

1.0

Signal Noise Immunity, VNOISE

Noise glitches from 10 MHz to

100 MHz, width up to 50 ns

300

p−p

Digital Input Logic Levels (TACH1 to TACH3)

Input High Voltage, VIH

Maximum input voltage

2.0

5.5

Input Low Voltage, VIL

Minimum input voltage

−0.3

0.8

Hysteresis

0.5

V p−p

Digital Input Logic Levels (THERM)

Input High Voltage, VIH

0.75 x VCCP

Input Low Voltage, VIL

0.4

Digital Input Current

Input High Current, IIH

VIN = VCC

±1

Input Low Current, IIL

VIN = 0

±1

Input Capacitance, CIN

5.0

Serial Bus Timing (Note 2)

(See Figure 2)

Clock Frequency, fSCLK

400

kHz

Glitch Immunity, tSW

Bus Free Time, tBUF

4.7

SCL Low Time, tLOW

4.7

SCL High Time, tHIGH

4.0

SCL, SDA Rise Time, tr

1000

SCL, SDA Fall Time, tf

300

Data Setup Time, tSU;DAT

250

Detect Clock Low Timeout, tTIMEOUT

Can be optionally disabled

1. All voltages are measured with respect to GND, unless otherwise specified. Typical voltages are TA = 25°C and represent a parametric norm.

Logic inputs accept input high voltages up to VMAX, even when the device is operating down to VMIN. Timing specifications are tested at logic

levels of VIL = 0.8 V for a falling edge, and VIH = 2.0 V for a rising edge.

2. Guaranteed by design, not production tested.

3. VTT is the voltage input on Pin 8. The VTT voltage is determined by the processor installed on the system.

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