© 2009 Microchip Technology, Inc.

DS41393A-Page 9

Figure 9 : I

Figure 10 : I

7.7.2

SPI

SPI operates in slave mode with an idle low SCK and data transmitted on the SCK falling edge.

The SIQ pin functions as an interrupt output. It is asserted high when data is available. The pin has a dual

purpose with driving an optional LED.

The SS pin is optional for “Slave Select” functionality. It is active (selects) when pulled low to VSS. Tie to VSS if

not used.

If data is clocked out when the controller has no valid data to provide, then 0x4d (ASCII "M") will be presented.

Timing diagrams are shown below.

Figure 11 : SPI Timing Diagram – Bit Timing