HT86AR72 datasheet(49/68 Pages) HOLTEK

49 / 68 page

HT86Axx/HT86ARxx

Rev. 1.00

March 19, 2010

The CSEN bit in the SBCR register controls the overall

function of the SPI interface. Setting this bit high, will en-

able the SPI interface by allowing the SCS line to be ac-

tive, which can then be used to control the SPI interface.

If the CSEN bit is low, the SPI interface will be disabled

and the SCS line will be in a floating condition and can

therefore not be used for control of the SPI interface.

The SBEN bit in the SBCR register must also be high

which will place the SDI line in a floating condition and

the SDO line high. If in Master Mode the SCK line will be

either high or low depending upon the clock polarity con-

figuration option. If in Slave Mode the SCK line will be in

a floating condition. If SBEN is low then the bus will be

disabled and SCS, SDI, SDO and SCK will all be in a

floating condition.

In the Master Mode the Master will always generate the

clock signal. The clock and data transmission will be ini-

tiated after data has been written to the SBDR register.

In the Slave Mode, the clock signal will be received from

an external master device for both data transmission or

reception. The following sequences show the order to

be followed for data transfer in both Master and Slave

Mode:

· Master Mode

Step 1. Select the clock source using the CKS bit in

the SBCR control register

Step 2. Setup the M0 and M1 bits in the SBCR control

required Baud rate. Values of 00, 01 or 10 can

be selected.

Step 3. Setup the CSEN bit and setup the MLS bit to

choose if the data is MSB or LSB first,

this must be same as the Slave device.

Step 4. Setup the SBEN bit in the SBCR control

Step 5. For write operations: write the data to the

SBDR register, which will actually place the

data into the TXRX buffer. Then use the SCK

and SCS lines to output the data.

Goto to step6.For read operations: the data

transferred in on the SDI line will be stored

in the TXRX buffer until all the data has been

received at which point it will be latched into

the SBDR register.

Step 6. Check the WCOL bit, if set high then a

collision error has occurred so return to step5.

If equal to zero then go to the following step.

Step 7. Check the TRF bit or wait for an SBI serial bus.

Step 8. Read data from the SBDR register.

Step 9. Clear TRF.

Step10. Goto step 5.

· Slave Mode

Step 1. The CKS bit has a don

¢t care value in the

slave mode.

Step 2. Setup the M0 and M1 bits to 00 to select the

Slave Mode. The CKS bit is don

¢t care.

Step 3. Setup the CSEN bit and setup the MLS bit to

choose if the data is MSB or LSB first,

this must be same as the Master device.

Step 4. Setup the SBEN bit in the SBCR control

Step 5. For write operations: write data to the SBCR

the TXRX register, then wait for the master

clock and SCS signal. After this goto step 6.

For read operations: the data transferred in

on the SDI line will be stored in the TXRX

buffer until all the data has been received

at which point it will be latched into the SBDR

Step 6. Check the WCOL bit, if set high then a

collision error has occurred so return to step5.

If equal to zero then go to the following step.

Step 7. Check the TRF bit or wait for an SBI serial bus.

Step 8. Read data from the SBDR register.

Step 9. Clear TRF

Step10. Goto step 5

SPI Configuration Options

Several configuration options exist for the SPI Interface

function which must be setup during device program-

ming. The first is a configuration to select the PD0~PD3

pins to be used as the SPI interface pins. Another option

is to enable the operation of the WCOL, write collision

bit, in the SBCR register. Another option exists to select

the clock polarity of the SCK line. A configuration option

also exists to disable or enable the operation of the

CSEN bit in the SBCR register. If the configuration op-

tion disables the CSEN bit then this bit cannot be used

to affect overall control of the SPI Interface.

Error Detection

The WCOL bit in the SBCR register is provided to indi-

cate errors during data transfer. The bit is set by the Se-

rial Interface but must be cleared by the application

program. This bit indicates a data collision has occurred

which happens if a write to the SBDR register takes

place during a data transfer operation and will prevent

the write operation from continuing. The bit will be set

high by the Serial Interface but has to be cleared by the

user application program. The overall function of the

WCOL bit can be disabled or enabled by a configuration

option.

Programming Considerations

When the device is placed into the Power Down Mode

note that data reception and transmission will continue.

The TRF bit is used to generate an interrupt when the

data has been transferred or received.

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