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Copyright © 2010 Future Technology Devices International Limited

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Document Reference No.: FT_000016

VDIP1 Vinculum VNC1L Module Datasheet Version 1.01

Clearance No.: FTDI# 131

3.7.2 Timing Diagram - Parallel FIFO Write Transaction

When in parallel FIFO interface mode, the timing of a write operation is shown in Figure 3.7 and Table

3.10

Figure 3.7 - FIFO Write Cycle.

Time

Description

Min

Max

Unit

T7

WR Active Pulse Width

50

-

ns

T8

WR to WR Pre-Charge Time

50

-

ns

T9

WR Active to Valid Data

20

-

ns

T10

Data Hold Time from WR

Inactive*

0

-

ns

T11

WR Inactive to TXE#

5

25

ns

T12

TXE# Inactive After WR Cycle

80

-

ns

Table 3.10 - FIFO Write Cycle Timing