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XIO2001 Folha de dados(PDF) 9 Page - Texas Instruments

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Nome de Peças XIO2001
Descrição Electrónicos  PCI Express??to PCI Bus Translation Bridge
PDF  128 Pages
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Fabricante Electrônico  TI [Texas Instruments]
Página de início  http://www.ti.com
Logo TI - Texas Instruments

XIO2001 Folha de dados(HTML) 9 Page - Texas Instruments

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XIO2001
www.ti.com
SCPS212D – MAY 2009 – REVISED JANUARY 2010
XIO2001 PCI Express™ to PCI Bus Translation Bridge
Check for Samples: XIO2001
1
Introduction
1.1
Features
1
234
Prioritization Scheme
• Full ×1 PCI Express Throughput
• Two Package Options: 12 mm × 12 mm and 7
• Fully Compliant with PCI Express to PCI/PCI-X
mm × 7 mm
Bridge Specification, Revision 1.0
• Internal PCI Arbiter Supporting Up to 6 External
• Fully Compliant with PCI Express Base
PCI Masters
Specification, Revision 2.0
• Advanced PCI Express Message Signaled
• Fully Compliant with PCI Local Bus
Interrupt Generation for Serial IRQ Interrupts
Specification, Revision 2.3
• External PCI Bus Arbiter Option
• PCI Express Advanced Error Reporting
Capability Including ECRC Support
• PCI Bus LOCK Support
• Support for D1, D2, D3hot, and D3cold
• JTAG/BS for Production Test
• Active-State Link Power Management Saves
• PCI-Express CLKREQ Support
Power When Packet Activity on the PCI
• Clock Run and Power Override Support
Express Link is Idle, Using Both L0s and L1
• Six Buffered PCI Clock Outputs (25 MHz, 33
States
MHz, 50 MHz, or 66 MHz)
• Wake Event and Beacon Support
• PCI Bus Interface 3.3-V and 5.0-V (25 MHz or 33
• Error Forwarding Including PCI Express Data
MHz only at 5.0 V) Tolerance Options
Poisoning and PCI Bus Parity Errors
• Integrated AUX Power Switch Drains VAUX
• Utilizes 100-MHz Differential PCI Express
Power Only When Main Power Is Off
Common Reference Clock or 125-MHz
• Five 3.3-V, Multifunction, General-Purpose I/O
Single-Ended, Reference Clock
Terminals
• Optional Spread Spectrum Reference Clock is
• Memory-Mapped EEPROM Serial-Bus
Supported
Controller Supporting PCI Express Power
• Robust Pipeline Architecture To Minimize
Budget/Limit Extensions for Add-In Cards
Transaction Latency
• Compact Footprint, Lead-Free 144-Ball, ZAJ
• Full PCI Local Bus 66-MHz/32-Bit Throughput
MicroStar™ BGA, Lead-Free 169-Ball ZGU
• Support for Six Subordinate PCI Bus Masters
MicroStar BGA, and PowerPad™ HTQFP
with Internal Configurable, 2-Level
128-Pin PNP Package
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2
PowerPad, MicroStar are trademarks of Texas Instruments.
3
PCI Express is a trademark of PCI-SIG.
4
All other trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Copyright © 2009–2010, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.



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