CS5525 CS5526

6

DS202F5

Notes: 19. Device parameters are specified with a 32.768 kHz clock; however, clocks up to 100 kHz can be used

for increased throughput.

20. Specified using 10% and 90% points on waveform of interest. Output loaded with 50 pF.

21. Oscillator start-up time varies with crystal parameters. This specification does not apply when using an

external clock source.

22. Applicable when SCLK is continuously running.

Parameter

Symbol

Min

Typ

Max

Unit

Master Clock Frequency

(Note 19)

Internal Clock

External Clock

XIN

30

30

32.768

32.768

36

100

kHz

Master Clock Duty Cycle

40

-

60

%

Rise Times

(Note 20)

Any Digital Input Except SCLK

SCLK

Any Digital Output

-

-

-

-

-

50

1.0

100

-

µs

µs

ns

Fall Times

(Note 20)

Any Digital Input Except SCLK

SCLK

Any Digital Output

-

-

-

-

-

50

1.0

100

-

µs

µs

ns

Start-up

Oscillator Start-up Time

XTAL = 32.768 kHz

(Note 21)

-500-

ms

Power-on Reset Period

-

1003

-

XIN

cycles

Serial Port Timing

Serial Clock Frequency

SCLK

0

-

2

MHz

SCLK Falling to CS Falling for continuous running SCLK

(Note 22)

100

-

-

ns

Serial Clock

Pulse Width High

Pulse Width Low

250

250

-

-

-

-

ns

ns

SDI Write Timing

CS Enable to Valid Latch Clock

50

-

-

ns

Data Set-up Time prior to SCLK rising

50

-

-

ns

Data Hold Time After SCLK Rising

100

-

-

ns

SCLK Falling Prior to CS Disable

100

-

-

ns

SDO Read Timing

CS to Data Valid

--

150

ns

SCLK Falling to New Data Bit

--

150

ns

CS Rising to SDO Hi-Z

--

150

ns