PixArt Imaging Inc.

PAS005B

CMOS Image Sensor IC

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PixArt Imaging Inc.

Fig 5.2 Valid Data

5.2 Data Transfer Format

5.2.1 Master transmits data to slave (write cycle)

S : Start

A : Acknowledge by slave

P : Stop

RW : The LSB of 1

RW=1 read cycle, RW=0 write cycle.

SUBADDRESS : The address values of PAS005B internal control registers

(Please refer to PAS005B register description)

S

SLAVE ID (7 BIT)

RW

A

SUBADDRESS (8 BIT)

A

DATA

P

A

1ST BYTE

2ND BYTE

n BYTEs + A

MSB

LSB=0

A

DATA

DATA

STABLE

DATA

CHANGE

ALLOWED

SDA

SCL

During write cycle, the master generates start condition and then places the 1

slave address (7 bits) with a read/write control bit to SDA line. After slave(PAS005B) issues acknowledgment,

the master places 2

master places the 8 bits data on SDA line and transmit to PAS005B control register (address was assigned by

2

cycle. In the condition of multi-byte write, the PAS005B sub-address is automatically increment after each

DATA byte transferred. The data and A cycles is repeat until last byte write. Every control registers value

inside PAS005B can be programming via this way. (Please refer to Fig 5.3.)