MCP6281-ESLASHMS datasheet(13/36 Pages) MICROCHIP

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DS21811E-page 13

MCP6281/1R/2/3/4/5

4.2

Rail-to-Rail Output

The output voltage range of the MCP6281/1R/2/3/4/5

op amp is VDD –15mV (min.) and VSS +15mV (max.)

when

RL =10kΩ is connected to VDD/2 and

VDD = 5.5V. Refer to Figure 2-16 for more information.

4.3

Capacitive Loads

Driving large capacitive loads can cause stability

problems for voltage feedback op amps. As the load

capacitance increases, the feedback loop’s phase

margin decreases and the closed-loop bandwidth is

reduced. This produces gain peaking in the frequency

response, with overshoot and ringing in the step

response. A unity-gain buffer (G = +1) is the most

sensitive to capacitive loads, though all gains show the

same general behavior.

When driving large capacitive loads with these op

amps (e.g., > 100 pF when G = +1), a small series

resistor at the output (RISO in Figure 4-3) improves the

feedback loop’s phase margin (stability) by making the

output load resistive at higher frequencies. The

bandwidth will generally be lower than the bandwidth

with no capacitive load.

FIGURE 4-3:

Output Resistor, RISO

stabilizes large capacitive loads.

Figure 4-4 gives recommended RISO values for differ-

ent capacitive loads and gains. The x-axis is the

normalized load capacitance (CL/GN), where GN is the

circuit's noise gain. For non-inverting gains, GN and the

Signal Gain are equal. For inverting gains, GN is

1+|Signal Gain| (e.g., -1 V/V gives GN = +2 V/V).

FIGURE 4-4:

Recommended RISO Values

for Capacitive Loads.

After selecting RISO for your circuit, double-check the

resulting

frequency

response

peaking

and

step

response overshoot. Modify RISO's value until the

response is reasonable. Bench evaluation and simula-

tions with the MCP6281/1R/2/3/4/5 SPICE macro

model are helpful.

4.4

MCP628X Chip Select (CS)

The MCP6283 and MCP6285 are single and dual op

amps with Chip Select (CS), respectively. When CS is

pulled high, the supply current drops to 0.7 µA (typical)

and flows through the CS pin to VSS. When this hap-

pens, the amplifier output is put into a high-impedance

state. By pulling CS low, the amplifier is enabled. The

CS pin has an internal 5 M

Ω (typical) pull-down resistor

connected to VSS, so it will go low if the CS pin is left

floating. Figure 1-1 shows the output voltage and

supply current response to a CS pulse.

4.5

Cascaded Dual Op Amps

(MCP6285)

The MCP6285 is a dual op amp with Chip Select (CS).

The Chip Select input is available on what would be the

non-inverting input of a standard dual op amp (pin 5).

This pin is available because the output of op amp A

connects to the non-inverting input of op amp B, as

shown in Figure 4-5. The Chip Select input, which can

be connected to a microcontroller I/O line, puts the

device in Low-power mode. Refer to Section 4.4

“MCP628X Chip Select (CS)”.

FIGURE 4-5:

Cascaded Gain Amplifier.

The output of op amp A is loaded by the input imped-

ance of op amp B, which is typically 1013

Ω||6pF, as

specified in the DC specification table (Refer to

Section 4.3 “Capacitive Loads” for further details

regarding capacitive loads).

The common mode input range of these op amps is

specified in the data sheet as VSS – 300 mV and

VDD + 300 mV. However, since the output of op amp A

is limited to VOL and VOH (20 mV from the rails with a

10 k

Ω load), the non-inverting input range of op amp B

is limited to the common mode input range of

VSS + 20 mV and VDD –20mV.

VIN

RISO

VOUT

–

MCP628X

100

1,000

100

1,000

10,000

Normalized Load Capacitance; CL / GN (pF)

GN = 1 V/V

GN = 2 V/V

4 V/V

VINA+

VOUTB

MCP6285

VINA–

VOUTA/VINB+

VINB–

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