AS8228 datasheet(70/123 Pages) AMSCO

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Data Sheet AS8218 / AS8228

Revision 3.0, 31-May-06

Page 70 of 123

8.5

External EEPROM Requirements

An external EEPROM with SPI bus serial interface is used for non-volatile program and data storage. The SPI

master block that communicates with the EEPROM is specified above. This section explains the requirement

for Serial EEPROMs. It shows the most important figures and tables as a reference. For the details please turn

to the data sheet of your specifically applied EEPROM.

The following minimum requirements must be fulfilled:

Pins

There must be at least the typical SPI pins like

serial data input (EEP_SI), serial data output (EEP_SO)

serial clock input (EEP_SC), chip select input (EEP_S_N)

Clock Rate

The applicable clock rate pin EEP_SC must be

≥ 1MHz to allow correct bootloading for maximum mcu_clk =

4MHz.

Status Register

must look like this:

don’t care for AS8218 / AS8228 bootloader/SCT

Bit 0 must be the WIP bit, indicating that a write operation is in progress. Only this bit is polled during the

EEPROM upload, means programming of the EEPROM. The Status register can be accessed via the RDSR

instruction.

Data Protection

The write protection block size is given in the table below:

Status Register Bits

BP1

BP0

Protected Block

Array Addresses Protected

Example only

None

Upper quarter

6000h – 7FFFh

Upper half

4000h – 7FFFh

Whole memory

0000h – 7FFFh

Note: The array addresses must be referenced from the data sheet of the specific EEPROM used.

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