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AS5311ASST Folha de dados(PDF) 9 Page - ams AG |
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AS5311ASST Folha de dados(HTML) 9 Page - ams AG |
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9 / 23 page ![]() AS5311 Data Sheet www.austriamicrosystems.com Revision 1.01 9 - 23 Parameter Symbol Min Typ Max Unit Note Integral non-linearity (over temperature) INLtemp ± 10 μm Maximum error with respect to the best line fit. Ideal magnet Tamb = -30 to +70 °C. Differential non-linearity DNL ±0.97 μm 10bit, no missing codes Transition noise TN 0.6 μm RMS 1 sigma Power-on reset thresholds On voltage; 300mV typ. hysteresis Off voltage; 300mV typ. hysteresis Von Voff 1.37 1.08 2.2 1.9 2.9 2.6 V DC supply voltage 3.3V (VDD3V3) DC supply voltage 3.3V (VDD3V3) Power-up time tPwrUp 20 ms Until status bit OCF = 1 System propagation delay absolute output : tdelay 96 µs Delay of ADC, DSP and absolute interface System propagation delay incremental output tdelay 384 µs Including interpolation delay at high speeds 9.90 10.42 10.94 Tamb = 25°C Internal sampling rate for absolute output fS 9.38 10.42 11.46 kHz Tamb = -40 to +125°C, Hysteresis, incremental outputs Hyst 2 LSB No Hysteresis at absolute serial outputs Read-out frequency CLK 1 MHz Max. clock frequency to read out serial data Integral Non-Linearity (INL) is the maximum deviation between actual position and indicated position. Differential Non-Linearity (DNL) is the maximum deviation of the step length from one position to the next. Transition Noise (TN) is the repeatability of an indicated position. 6.6 Timing Characteristics 6.6.1 Synchronous Serial Interface (SSI) Operating conditions: Tamb = -40 to +125°C, VDD5V = 3.0~3.6V (3V operation) VDD5V = 4.5~5.5V (5V operation) unless otherwise noted. Parameter Symbol Min Typ Max Unit Note Data output activated (logic high) t DO active 100 ns Time between falling edge of CSn and data output activated First data shifted to output register tCLK FE 500 ns Time between falling edge of CSn and first falling edge of CLK Start of data output T CLK / 2 500 ns Rising edge of CLK shifts out one bit at a time Data output valid t DO valid 413 ns Time between rising edge of CLK and data output valid Data output tristate t DO tristate 100 ns After the last bit DO changes back to “tristate” Pulse width of CSn t CSn 500 ns CSn = high; To initiate read-out of next angular position Read-out frequency fCLK >0 1 MHz Clock frequency to read out serial data |
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