ST8024

Ver 2.1

Page 27/28

2009/08/19

14

APPLITION NOTE ( REFERENCE ONLY )

14.1 PCB and ITO layout notice:

Pin Name

ITO Resistor Values

LGND, GND, VDD, Vss

Less than 75

when VDD ≧ 3.0V, and the smaller the better

V0R, V0L

Less than 150 , and the smaller the better

V12R, V12L, V34R, V12L

Less than 250 , and the smaller the better

PS : Above resistor value test on 3” LCD panel.

14.2 We suggest the ITO resistor for LCD panel is less than 15Ω/Square, and the resistor value is as

smaller as better.

14.3 Adjust V1 and V4 voltage to keep the V0-V1 = V4-VSS relation to get better display quality. The

(V0-V1)-(V4-VSS) value had better less than 100mV.

14.4 Add 0.1uF high frequency by-pass capacitor to filter the noise on V0~V4 to VSS.

14.5 When OP follower circuit is used, please be sure the OP power is higher than V0 at least 1.5V.

14.6 EIO1 and EIO2 is enable pin for driver, please pay attention to the distance to avoid noise when

cascade function is used. Two chip connecting distance is as shorter as better.