AT86RF212 datasheet(2/171 Pages) ATMEL

2 / 171 page

8168B-MCU Wireless-02/09

AT86RF212

1 Overview

The AT86RF212 is a low-power, low-voltage 700/800/900 MHz transceiver specially

designed for the IEEE Standard 802.15.4, ZigBee, 6LoWPAN, and high data rate ISM

applications. For the sub-1 GHz bands, it supports low data rates (20 and 40 kbit/s) of

the IEEE Standard 802.15.4-2003 [2] and provides optional data rates (100 and 250

kbit/s) using O-QPSK, according to the IEEE Standard 802.15.4-2006 [1] and the

respective IEEE P802.15.4c Draft Amendment [3]. Furthermore, proprietary High Data

Rate Modes up to 1000 kbit/s can be employed.

The AT86RF212 is a true SPI-to-antenna solution. RF-critical components except the

antenna, crystal, and de-coupling capacitors are integrated on-chip. MAC and AES

hardware accelerators improve overall system power efficiency and timing.

1.1 General Circuit Description

The AT86RF212 single-chip RF transceiver provides a complete radio interface

between the antenna and the microcontroller. It comprises the analog radio part, digital

modulation and demodulation including time and frequency synchronization, as well as

data buffering. The number of external components is minimized so that only the

antenna, a filter (at high output power levels), the crystal, and four bypass capacitors

are required. The bidirectional differential antenna pins are used in common for RX and

TX, i.e. no external antenna switch is needed. Control of an external power amplifier is

supported by two digital control signals (differential operation). The transceiver block

diagram is shown in Figure 1-1.

The receiver path is based on a low-IF architecture. After channel filtering and down-

conversion the low-IF signal is sampled and applied to the digital signal processing part.

Communication between transmitter and receiver is based on direct sequence spread

spectrum with different modulation schemes and spreading codes. The AT86RF212

supports the IEEE 802.15.4-2006 standard mandatory BPSK modulation and optional

O-QPSK modulation in the 868.3 MHz and 915 MHz bands. In addition it supports the

O-QPSK modulation defined in IEEE P802.15.4c for the Chinese 780 MHz band.

For applications not necessarily targeting IEEE compliant networks the radio

transceiver supports proprietary High Data Rate Modes based on O-QPSK.

A single 128 byte TRX buffer stores receive or transmit data.

The AT86RF212 features hardware supported 128 bit security operation. The

standalone AES encryption/decryption engine can be accessed in parallel to all PHY

operational modes. Configuration of the AT86RF212, reading, and writing of data

memory as well as the AES hardware engine are controlled by the SPI interface and

additional control signals.

On-chip low-dropout voltage regulators provide the analog and digital 1.8 V power

supply. Control registers retain their settings in SLEEP mode when the regulators are

turned off. The RX and TX signal processing paths are highly integrated and optimized

for low power consumption.

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