ATmega64A datasheet(71/392 Pages) ATMEL

71 / 392 page

8160C–AVR–07/09

ATmega64A

Figure 13-3. Synchronization when Reading an Externally Applied Pin Value

Consider the clock period starting shortly after the first falling edge of the system clock. The latch

is closed when the clock is low, and goes transparent when the clock is high, as indicated by the

shaded region of the “SYNC LATCH” signal. The signal value is latched when the system clock

goes low. It is clocked into the PINxn Register at the succeeding positive clock edge. As indi-

cated by the two arrows t

pd,max and tpd,min, a single signal transition on the pin will be delayed

between ½ and 1-½ system clock period depending upon the time of assertion.

When reading back a software assigned pin value, a nop instruction must be inserted as indi-

cated in Figure 13-4. The out instruction sets the “SYNC LATCH” signal at the positive edge of

the clock. In this case, the delay t

pd through the synchronizer is one system clock period.

Figure 13-4. Synchronization when Reading a Software Assigned Pin Value

The following code example show how to set Port B pins 0 and 1 high, 2 and 3 low, and define

the port pins from 4 to 7 as input with pull-ups assigned to port pins 6 and 7. The resulting pin

SYSTEM CLK

INSTRUCTIONS

SYNC LATCH

PINxn

r17

in r17, PINx

0xFF

0x00

tpd, max

XXX

tpd, min

nop

in r17, PINx

0xFF

0x00

0xFF

tpd

out PORTx, r16

SYSTEM CLK

r16

INSTRUCTIONS

SYNC LATCH

PINxn

r17

ATmega64A Folha de dados(PDF) 71 Page - ATMEL Corporation