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ST7263BEx Folha de dados(PDF) 62 Page - STMicroelectronics

Nome de Peças ST7263BEx
Descrição Electrónicos  Low speed USB 8-bit MCU family with up to 32 KB Flash/ROM, DFU capability, 8-bit ADC, WDG, timer, SCI and I²C
PDF  186 Pages
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Fabricante Electrônico  STMICROELECTRONICS [STMicroelectronics]
Página de início  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

ST7263BEx Folha de dados(HTML) 62 Page - STMicroelectronics

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On-chip peripherals
ST7263Bxx
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Doc ID 7516 Rev 8
A minimum of four falling edges of the CPU clock must occur between two consecutive
active edges of the external clock; thus the external clock frequency must be less than a
quarter of the CPU clock frequency.
Figure 29.
Counter timing diagram, internal clock divided by 2
1.
The MCU is in reset state when the internal reset signal is high, when it is low the MCU is running.
Figure 30.
Counter timing diagram, internal clock divided by 4
1.
The MCU is in reset state when the internal reset signal is high, when it is low the MCU is running.
Figure 31.
Counter timing diagram, internal clock divided by 8
1.
The MCU is in reset state when the internal reset signal is high, when it is low the MCU is running.
CPU CLOCK
FFFD FFFE FFFF 0000
0001
0002
0003
INTERNAL RESET
TIMER CLOCK
COUNTER REGISTER
TIMER OVERFLOW FLAG (TOF)
FFFC
FFFD
0000
0001
CPU CLOCK
INTERNAL RESET
TIMER CLOCK
COUNTER REGISTER
TIMER OVERFLOW FLAG (TOF)
CPU CLOCK
INTERNAL RESET
TIMER CLOCK
COUNTER REGISTER
TIMER OVERFLOW FLAG (TOF)
FFFC
FFFD
0000



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