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ADCLK946/PCBZ Folha de dados(PDF) 11 Page - Analog Devices

Nome de Peças ADCLK946/PCBZ
Descrição Electrónicos  Six LVPECL Outputs, SiGe Clock Fanout Buffer
PDF  12 Pages
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Fabricante Electrônico  AD [Analog Devices]
Página de início  http://www.analog.com
Logo AD - Analog Devices

ADCLK946/PCBZ Folha de dados(HTML) 11 Page - Analog Devices

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ADCLK946
Rev. 0 | Page 11 of 12
VREF
INPUT TERMINATION OPTIONS
VCC
VT
CLK
VREF
VT
CLK
CONNECT VT TO VCC.
50Ω
50Ω
Figure 19. Interfacing to CML Inputs
VREF
VT
CONNECT VT TO VCC − 2V.
CLK
VCC – 2V
50Ω
50Ω
CLK
Figure 20. Interfacing to PECL Inputs
CONNECT VT TO VREF.
50Ω
50Ω
CLK
CLK
VREF
VT
Figure 21. AC-Coupling Differential Signals Inputs, Such as LVDS
CONNECT VT, VREF, AND CLK. PLACE A BYPASS
CAPACITOR FROM VT TO GROUND.
ALTERNATIVELY, VT, VREF, AND CLK CAN BE
CONNECTED, GIVING A CLEANER LAYOUT AND
A 180°
50Ω
50Ω
CLK
CLK
PHASE SHIFT.
Figure 22. Interfacing to AC-Coupled Single-Ended Inputs



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