TMC2192 datasheet(39/69 Pages) CADEKA

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PRODUCT SPECIFICATION

TMC2192

REV. 1.0.0 8/13/03

Control Register Deﬁnitions (continued)

Horizontal Ancillary Data Control Register (0x07)

76543210

LDFID

SKFLIP

DDSRST

RESERVED

ANCFREN

ANCPHEN

ANCTREN

Reg

Bit

Name

Description

LDFID

Field Lock Select. When LDFID is HIGH, the FLD[2:0] pins are used as

inputs to lock the field the that the TMC2192 is encoding. 5 PXCK’s after

the falling edge of HSIN the FLD[2:0] pins are sampled. When LDFID is

LOW, the FLD[2:0] pins output the current field that is being encoded.

SKFLIP

Soft Key Inversion.

When SKFLP is LOW, the key generated by the data keying is a normal

state. When SKFLP is HIGH, the key generated by the data keying is a

inverted state.

DDSRST

DDS Reset. By inserting a logic HIGH into this register the DDS

accumulator is reset to SYSPH value at the start of the next field 1 and

DDSRST is reset LOW. This enables the DDS to be reset when the

encoder is operating with a free running subcarrier.

4-3

RESERVED

ANCFREN

Ancillary Frequency Enable.

When HIGH, the encoder gets subcarrier frequency data (FREQ3-0) from

incoming ancillary data (in accordance with FRV bit). When LOW,

FREQ3-0 registers contain the subcarrier frequency data.

ANCPHEN

Ancillary Phase Enable.

When HIGH, the encoder gets subcarrier phase offset data (SCHPHL and

SCHPHM) from incoming ancillary data (in accordance with PHV bit).

When LOW, a default value of 0000h is used for subcarrier phase.

ANCTREN

Ancillary Timing Enable.

When HIGH, the encoder decodes incoming ancillary data to determine

video timing (FIELD and SVF). When LOW, the ancillary timing reference

data is ignored.

Ancillary Data ID Register (0x08)

76543210

ANCID

Reg

Bit

Name

Description

7-0

ANCID

Ancillary Data Identification.

Bits 7-0 determine the ancillary data identification. Bit 0 is an odd parity bit.

The value in this register must match that of the incoming ancillary data.

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