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SPT9101SCU Folha de dados(PDF) 6 Page - Cadeka Microcircuits LLC. |
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SPT9101SCU Folha de dados(HTML) 6 Page - Cadeka Microcircuits LLC. |
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6 / 8 page ![]() 6 12/30/99 SPT9101 The RTN pin may be tied to an external voltage to generate an offset at the output. VOut must be kept to less than ±2.7 V typical output swing. VOut, with an external reference voltage at the RTN pin, is represented by the following formula: VOut = 4 VIN - 3 VRef where VRef = voltage at RTN pin and | VOut | ≤ 2.7 V The following options are generally not recommended due to the possibility of degraded noise performance of the device: the RTN pin can also be tied to an external resistor to reduce the gain but performance may degrade due to increased noise from the external resistor. Also RTN can be left open for unity gain mode, however, noise will increase. In all cases, VIN must be kept to -0.5 V≤ VIN ≤ +0.5 V for rated performance. SAMPLER FOR 12-BIT ADC APPLICATION The SPT9101 was specifically designed for applications where improved bandwidth performance is required. Figure 3 shows as simple block diagram of the SPT9101 as a sampler ahead of the SPT7922 12-bit, 30 MSPS ADC. Figure 3 - Sampler for 12-Bit ADC SPT9101 SPT7922 VIN Clock 1 Clock 2 12 The graph below entitled Improved Dynamic Performance Using the SPT9101 shows the performance with and without the SPT9101. The SPT9101 significantly extends the dy- namic performance range of the converter. PERFORMANCE CHARACTERISTICS SPT9101 Hold Mode Distortion vs. Temperature -65 -60 -50 -25 0 25 50 75 100 Temperature (°C) Worst Harmonic Input Frequency = 50 MHz Clock Frequency = 100 MHz Hold = 4 ns Track = 6 ns SPT9101 Hold Mode Distortion vs Input Frequency -75 -70 -65 -60 -55 1 10 100 Input Frequency (MHz) Worst Harmonic Clock Frequency = 100 MHz Track = 6 ns Hold = 4 ns Improved Dynamic Performance Using the SPT9101 510 15 20 40 50 60 70 FIN (MHz) SPT7922 SPT9101 & SPT7922 (FS = 28 MSPS) Droop Rate vs Temperature -20 0 2040 6080 Temperature (°C) -40 0 40 -80 -120 |
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