LTM9002 datasheet(6/28 Pages) LINER

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LTM9002

9002f

Note 1: Stresses beyond those listed under Absolute Maximum Ratings

may cause permanent damage to the device. Exposure to any Absolute

Maximum Rating condition for extended periods may affect device

reliability and lifetime.

Note 2: All voltage values are with respect to ground with GND and OGND

wired together (unless otherwise noted).

Note 3: OVDD = VCC = VDD = 3V, fSAMPLE = MAX, input range = VIN

with differential drive, CLKA = CLKB, VINCM = 1.25V, AMPSHDN =

ADCSHDN = 0V, unless otherwise noted.

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

Sampling Frequency

LTM9002-AA

125

MHz

LTM9002-LA

MHz

CLK Low Time

Duty Cycle Stabilizer Off (Note 6), LTM9002-AA

Duty Cycle Stabilizer On (Note 6), LTM9002-AA

3.8

500

CLK High Time

Duty Cycle Stabilizer Off (Note 6), LTM9002-AA

Duty Cycle Stabilizer On (Note 6), LTM9002-AA

3.8

500

CLK Low Time

Duty Cycle Stabilizer Off (Note 6), LTM9002-LA

Duty Cycle Stabilizer On (Note 6), LTM9002-LA

7.3

7.7

500

CLK High Time

Duty Cycle Stabilizer Off (Note 6), LTM9002-LA

Duty Cycle Stabilizer On (Note 6), LTM9002-LA

7.3

7.7

500

tAP

Absolute Aperture Delay

0ns

CLK to DATA Delay

CL = 5pF (Note 6)

1.4

2.7

5.4

CLK to CLKOUT Delay

CL = 5pF (Note 6)

1.4

2.7

5.4

DATA to CLKOUT Skew

(tD – tC) (Note 6)

–0.6

0.6

tMD

MUX to DATA Delay

CL = 5pF (Note 6)

1.4

2.7

5.4

DATA Access Time After OE

↓

CL = 5pF (Note 6)

4.3

BUS Relinquish Time

(Note 6)

3.3

8.5

Pipeline Latency

Cycles

SPI Interface for Aux DACs, VDD = 2.7V to 3.6V

SDI Valid to SCK Setup

SDI Valid to SCK Hold

SCK High Time

9ns

SCK Low Time

9ns

CS/LD Pulse Width

LSB SCK High to CS/LD

CS/LD Low to SCK High

t10

CS/LD High to SCK Positive Edge

SCK Frequency 50% Duty Cycle

MHz

The

l denotes the speciﬁcations which apply over the full operating temperature

range, otherwise speciﬁcations are at TA = 25°C. (Note 6) (Not applicable for LTM9002-LA)

TIMING CHARACTERISTICS

Note 4: Integral nonlinearity is deﬁned as the deviation of a code from a

straight line passing through the actual endpoints of the transfer curve.

The deviation is measured from the center of the quantization band.

Note 5: Offset error is the output code resulting when the inputs are

shorted together. The output code is converted to millivolts.

Note 6: Guaranteed by design, not subject to test.

Note 7: VDD = 3V, fSAMPLE = MAX, input range = VIN with differential drive.

The supply current and power dissipation are the sum total for both

channels with both channels active.

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