LTM4609EVPBF datasheet(20/24 Pages) LINER

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LTM4609

4609fa

VOUT

COUT

VIN

RSENSE

PGND

SW1

SW2

PGND

SGND

CIN

4609 F15

KELVIN CONNECTIONS TO RSENSE

+–

APPLICATIONS INFORMATION

Layout Checklist/Example

The high integration of LTM4609 makes the PCB board

layout very simple and easy. However, to optimize its electri-

cal and thermal performance, some layout considerations

are still necessary.

• Use large PCB copper areas for high current path, includ-

ing VIN, RSENSE, SW1, SW2, PGND and VOUT. It helps to

minimize the PCB conduction loss and thermal stress.

• Place high frequency input and output ceramic capaci-

tors next to the VIN, PGND and VOUT pins to minimize

high frequency noise

• RouteSENSE– andSENSE+ leadstogetherwithminimum

PC trace spacing. Avoid sense lines passing through

noisy areas, such as switch nodes.

• Place a dedicated power ground layer underneath the

unit.

• To minimize the via conduction loss and reduce module

thermal stress, use multiple vias for interconnection

between the top layer and other power layers

• Do not put vias directly on pads, unless the vias are

capped.

• Use a separated SGND ground copper area for com-

ponents connected to signal pins. Connect the SGND

to PGND underneath the unit.

Figure 15. gives a good example of the recommended

layout.

Figure 15. Recommended PCB Layout

VOUT

PGOOD

FCB

RUN

SW1

COMP

SW2

INTVCC

RSENSE

EXTVCC

SENSE–

STBYMD

PLLFLTR

VFB

SGND

PLLIN

LTM4609

9mΩ

4.7μH

RFB

7.15k

1.5k

100μF

25V

4609 TA02

VOUT

12V

10A

CLOCK SYNC

VIN

PGND

VIN

12V TO 36V

0.1μF

10μF

50V

×2

ON/OFF

SENSE+

Figure 16. Buck Mode Operation with 12V to 36V Input

TYPICAL APPLICATIONS

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