TVP6000CPFP datasheet(39/57 Pages) TI

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2–27

Table 2–17. RCM1 Output Signals

RCM1A

RCM1B

PIN RCM1

DESCRIPTION

Vertical synchronization (default)

Frame synchronization

FSEQ

Field sequence. For NTSC, FSEQ is high in the first field of every four fields.

For PAL, FSEQ is high in the first field of every eight fields.

N/A

Reserved

Table 2–18 shows the operating modes of pin RCM2 as defined by the SCN (bit 0, subaddress 98), CBLFM2

(bit 6, subaddress 6D), CBLFV2 (bit 2, subaddress 6C), and HSINSEL bits (bit 5, subaddress 6C).

Table 2–18. RCM2 Pin Configurations

SCN

CBLFM2

CBLFV2

HSINSEL

RCM2 PIN

SIGNAL DESCRIPTION

SCN

CBLFM2

CBLFV2

HSINSEL

AS OUTPUT

AS INPUT

SIGNAL DESCRIPTION

HSO

No function

As an output, RCM2 is asserted between

BMRQ and EMRQ in every line including

VBI (sub-address 71–73)

CBNO

No function

As an output, RCM2 is asserted between

BMRQ and EMRQ in every line excluding

VBI.

CBNO

CBNI

As an input, RCM2 is used for composite

blanking. As an output, RCM2 is asserted

between BMRQ and EMRQ in every line

excluding VBI.

CBNO

No function

As an output, RCM2 is asserted between

BMRQ and EMRQ in every line excluding

VBI.

RQO

Reserved

As an output only. RCM2 is used as

request for pixels. When asserted, this

signal sources the pixel on the bus at the

clock edge and informs external logic to

output next pixel.

Table 2–19. Encoding Setting

L21ENA

L21ENB

LINE 21 ENCODING MODE

Line 21 encoding off

Enables encoding in first field (odd field)

Enables encoding in second field (even field)

Enables encoding both fields

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