TMS320F243 datasheet(94/116 Pages) TI

94 / 116 page

TMS320F243, TMS320F241

DSP CONTROLLERS

SPRS064B – DECEMBER 1997 – REVISED FEBRUARY 1999

POST OFFICE BOX 1443

• HOUSTON, TEXAS 77251–1443

external memory interface

read timings

switching characteristics over recommended operating conditions for an external memory

interface read (see Figure 38)

PARAMETER

MIN

MAX

UNIT

td(COL–CNTL)

Delay time, CLKOUT low to control valid

td(COL–CNTH) Delay time, CLKOUT low to control inactive

td(COL–A)RD

Delay time, CLKOUT low to address valid

td(COH–RDL)

Delay time, CLKOUT high to RD strobe active

td(COL–RDH)

Delay time, CLKOUT low to RD strobe inactive high

–4

td(COL–SL)

Delay time, CLKOUT low to STRB strobe active low

td(COL–SH)

Delay time, CLKOUT low to STRB strobe inactive high

th(A)COL

Hold time, address valid after CLKOUT low

–4

tsu(A)RD

Setup time, address valid before RD strobe active low

th(A)RD

Hold time, address valid after RD strobe inactive high

–1

timing requirements [H = 0.5tc(CO)] (see Figure 38)

MIN

MAX

UNIT

ta(A)

Access time, read data from address valid

2H–20

tsu(D)RD

Setup time, read data before RD strobe inactive high

th(D)RD

Hold time, read data after RD strobe inactive high

th(AIV-D)

Hold time, read data after address invalid

–3

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