TLC2932

HIGH-PERFORMANCE PHASE-LOCKED LOOP

SLAS097E – SEPTEMBER 1994 – REVISED MAY 1997

5

POST OFFICE BOX 655303

recommended operating conditions

PARAMETER

MIN

NOM

MAX

UNIT

Supply voltage VDD (each supply see Note 3)

VDD = 3 V

2.85

3

3.15

V

Supply voltage, VDD (each supply, see Note 3)

VDD = 5 V

4.75

5

5.25

V

Input voltage, VI (inputs except VCO IN)

0

VDD

V

Output current, IO (each output)

0

±2

mA

VCO control voltage at VCO IN

0.9

VDD

V

Lock frequency (

×1 output)

VDD = 3 V

14

21

MHz

Lock frequency (

×1 output)

VDD = 5 V

22

50

MHz

Lock frequency (

×1/2 output)

VDD = 3 V

7

10.5

MHz

Lock frequency (

×1/2 output)

VDD = 5 V

11

25

MHz

Bias resistor RBIAS

VDD = 3 V

2.2

3.3

4.3

k

Ω

Bias resistor, RBIAS

VDD = 5 V

1.5

2.2

3.3

k

Ω

NOTE 3: It is recommended that the logic supply terminal (LOGIC VDD) and the VCO supply terminal (VCO VDD) should be at the same voltage

and separated from each other.

(unless otherwise noted)

VCO section

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

VOH

High-level output voltage

IOH = – 2 mA

2.4

V

VOL

Low-level output voltage

IOL = 2 mA

0.3

V

VIT

Input threshold voltage at SELECT, VCO INHIBIT

0.9

1.5

2.1

V

II

Input current at SELECT, VCO INHIBIT

VI = VDD or GND

±1

µA

Zi(VCO IN)

Input impedance

VCO IN = 1/2 VDD

10

M

Ω

IDD(INH)

VCO supply current (inhibit)

See Note 4

0.01

1

µA

IDD(VCO)

VCO supply current

See Note 5

5

15

mA

NOTES:

4. Current into VCO VDD, when VCO INHIBIT = VDD, PFD is inhibited.

5. Current into VCO VDD, when VCO IN = 1/2 VDD, RBIAS = 3.3 kΩ, VCO INHIBIT = GND, and PFD is inhibited.

PFD section

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

VOH

High-level output voltage

IOH = – 2 mA

2.7

V

VOL

Low-level output voltage

IOL = 2 mA

0.2

V

IOZ

High-impedance-state output current

PFD INHIBIT = high,

VI = VDD or GND

±1

µA

VIH

High-level input voltage at FIN–A, FIN–B

2.7

V

VIL

Low-level input voltage at FIN–A, FIN–B

0.5

V

VIT

Input threshold voltage at PFD INHIBIT

0.9

1.5

2.1

V

Ci

Input capacitance at FIN–A, FIN–B

5

pF

Zi

Input impedance at FIN–A, FIN–B

10

M

Ω

IDD(Z)

High-impedance-state PFD supply current

See Note 6

0.01

1

µA

IDD(PFD)

PFD supply current

See Note 7

0.1

1.5

mA

NOTES:

6. Current into LOGIC VDD, when FIN–A, FIN–B = GND, PFD INHIBIT = VDD, no load, and VCO OUT is inhibited.

7. Current into LOGIC VDD, when FIN–A, FIN–B = 1 MHz (VI(PP) = 3 V, rectangular wave), NC = GND, no load, and VCO OUT is

inhibited.