SLES025A datasheet(18/114 Pages) TI

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2–4

2.2.1

Clock Generation

The TAS1020B requires an external 6-MHz crystal with load capacitors and PLL loop filter components to derive all

the clocks needed for both USB and codec operation. Figure 4–1 shows the connection of these components to the

TAS1020B. Figure 4–1 also shows a ground shield residing on the top layer of the PCB and underneath the crystal

and its load capacitors and the PLL components. The PLL is an analog PLL, and noise pickup in these components

can translate to phase jitter at the output of the PLL, which in turn can translate to distortion at the codec. A ground

shield is recommended to attenuate the digital noise components on the board as seen at the PLL.

The AVSS and AVDD pins on the TAS1020B are used exclusively to power the analog PLL. To maintain isolation from

the digital noise residing on a board, AVSS should be a separate ground plane that connects to the primary ground

plane (DGND) at a single point via a ferrite bead. The ferrite bead should exhibit around 9

Ω of impedance at 100 MHz.

AVDD should also be distinct from DVDD. A recommended architecture is to generate DVDD and AVDD from the same

regulator line, with each derived from a RC filter in series with the regulator output. It is finally recommended that the

ground shield for the crystal and its load capacitors and the PLL loop filter components be connected to AVSS at a

single point via a ferrite bead of the same type as above.

Using the low frequency 6-MHz crystal and generating the required higher frequency clocks internally in the

TAS1020B is a major advantage with regard to EMI.

2.2.2

Boot Process

The TAS1020B can boot from EEPROM or execute a host boot. Host boot will be used in the following circumstances:

•

No EEPROM is present.

•

An EEPROM is present, but does not contain a valid header.

•

An EEPROM is present, but is a device EEPROM (contains header information only).

2.2.2.1 EEPROM Boot Process

If the target device has an application EEPROM (an EEPROM that contains both header and application data), and

if the header portion of the EEPROM content is valid, the EEPROM application code is downloaded to on-chip RAM.

During the download process, the RAM is mapped to data space, and the boot code that orchestrates the download

is part of the on-chip firmware housed in on-chip ROM. Also, while the application code is being downloaded, the

TAS1020B remains disconnected from the USB bus.

When the download is complete, the firmware sets the ROM disable bit SDW. The setting of this bit maps the RAM

from data space to program space, starting address 0x0000. Having set bit SDW, the firmware then branches to

address 0x0000, which is the reset entry point for the application code. The application code is now running.

The application code then switches on the PUR output. The PUR output pin is connected, through a resistor, to the

positive (DP) line of the differential USB bus. Switching PUR on informs the host that a full speed (12 Mb/s) device

is present on the bus. In the enumeration procedure that follows, the application code reports its run-time device

descriptor set. Following enumeration, the device is actively running its application.

2.2.2.2 Host Boot Process

The DFU code in the TAS1020B fully adheres to the USB Device Class Specification for DFU 1.0. In addition, the

TAS1020B utilizes the communication protocols from the DFU specification to implement a host boot capability for

those applications that do not have an EEPROM resource. In such cases, the TAS1020B, at power-up, reports its

DFU mode descriptor set rather than its run-time descriptor set and directly enters what the DFU specification terms

the DFU Program Mode. The host processor must be cognizant of the fact that the device under enumeration does

not have an EEPROM resource with valid code, and is already in the DFU mode awaiting a download per the DFU

protocol. All of this capability is provided by the ROM-based code (firmware) that resides on the TAS1020B.

Specifically, the host boot process addresses three cases—an EPROM is not present, an EEPROM is present but

the data in the EEPROM is invalid, or an EEPROM is present but the EEPROM is a device EEPROM (contains only

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