CLC2050 datasheet(12/17 Pages) CADEKA

12 / 17 page

Data Sheet

www.cadeka.com

Layout Considerations

General layout and supply bypassing play major roles in

high frequency performance. CaDeKa has evaluation

boards to use as a guide for high frequency layout and as

an aid in device testing and characterization. Follow the

steps below as a basis for high frequency layout:

• Include 6.8µF and 0.1µF ceramic capacitors for power

supply decoupling

• Place the 6.8µF capacitor within 0.75 inches of the power pin

• Place the 0.1µF capacitor within 0.1 inches of the power pin

• Remove the ground plane under and around the part,

especially near the input and output pins to reduce para-

sitic capacitance

• Minimize all trace lengths to reduce series inductances

Refer to the evaluation board layouts below for more in-

formation.

Evaluation Board Information

The following evaluation boards are available to aid in the

testing and layout of these devices:

Evaluation Board #

Products

CEB002

CLC1050

CEB006

CLC2050

CEB018

CLC4050

Evaluation Board Schematics

Evaluation board schematics and layouts are shown in Fig-

ures 7-14. These evaluation boards are built for dual- sup-

ply operation. Follow these steps to use the board in a

single-supply application:

1. Short -Vs to ground.

2. Use C3 and C4, if the -VS pin of the amplifier is not

directly connected to the ground plane.

Figure 7. CEB002 Schematic

Figure 8. CEB002 Top View

CLC2050 Folha de dados(PDF) 12 Page - Cadeka Microcircuits LLC.