CLC2011ISO8X datasheet(11/16 Pages) CADEKA

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Figure 7. Overdrive Recovery

Layout Considerations

General layout and supply bypassing play major roles in

high frequency performance. CaDeKa has evaluation

boards to use as a guide for high frequency layout and as

an aid in device testing and characterization. Follow the

steps below as a basis for high frequency layout:

• Include 6.8µF and 0.1µF ceramic capacitors for power

supply decoupling

• Place the 6.8µF capacitor within 0.75 inches of the power pin

• Place the 0.1µF capacitor within 0.1 inches of the power pin

• Remove the ground plane under and around the part,

especially near the input and output pins to reduce para-

sitic capacitance

• Minimize all trace lengths to reduce series inductances

Refer to the evaluation board layouts below for more in-

formation.

Evaluation Board Information

The following evaluation boards are available to aid in the

testing and layout of these devices:

Evaluation Board #

Products

CEB011

CLC1011 in SC70

CEB002

CLC1011 in SOT23

CEB006

CLC2011 in SOIC

CEB010

CLC2011 in MSOP

CEB018

CLC4011 in SOIC

CEB017

CLC4011 in TSSOP

Evaluation Board Schematics

Evaluation board schematics and layouts are shown in Fig-

ures 8-14. These evaluation boards are built for dual- sup-

ply operation. Follow these steps to use the board in a

single-supply application:

1. Short -Vs to ground.

2. Use C3 and C4, if the -VS pin of the amplifier is not

directly connected to the ground plane.

Figure 8. CEB002 Schematic

Figure 9. CEB002 Top View

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