CDK1308 datasheet(13/14 Pages) CADEKA

13 / 14 page

www.cadeka.com

ADVANCE Data Sheet

The quality of the input clock is extremely important for

high-speed, high-resolution ADCs. The contribution to SNR

from clock jitter with a full scale signal at a given frequency

is shown in the equation below:

SNRjitter = 20 • log (2 • π • FIN •

εt)

where FIN is the signal frequency, and

εt is the total rms

jitter measured in seconds. The rms jitter is the total of all

jitter sources including the clock generation circuitry, clock

distribution and internal ADC circuitry.

For applications where jitter may limit the obtainable per-

formance, it is of utmost importance to limit the clock

jitter. This can be obtained by using precise and stable

clock references (e.g. crystal oscillators with good jitter

specifications) and make sure the clock distribution is

well controlled. It might be advantageous to use analog

power and ground planes to ensure low noise on the sup-

plies to all circuitry in the clock distribution. It is of utmost

importance to avoid crosstalk between the ADC output bits

and the clock and between the analog input signal and

the clock since such crosstalk often results in harmonic

distortion.

The jitter performance is improved with reduced rise and

fall times of the input clock. Hence, optimum jitter per-

formance is obtained with LVDS or LVPECL clock with fast

edges. CMOS and sine wave clock inputs will result in

slightly degraded jitter performance.

If the clock is generated by other circuitry, it should be re-

timed with a low jitter master clock as the last operation

before it is applied to the ADC clock input.

Digital Outputs

Digital output data are presented on parallel CMOS form.

The voltage on the OVDD pin set the levels of the CMOS

outputs. The output drivers are dimensioned to drive a

wide range of loads for OVDD above 2.25V, but it is rec-

ommended to minimize the load to ensure as low transient

switching currents and resulting noise as possible. In ap-

plications with a large fanout or large capacitive loads, it

is recommended to add external buffers located close to

the ADC chip.

The timing is described in the Timing Diagram section.

Note that the load or equivalent delay on CK_EXT always

should be lower than the load on data outputs to ensure

sufficient timing margins.

The digital outputs can be set in tristate mode by setting

the OE_N signal high.

The CDK1308 employs digital offset correction. This means

that the output code will be 4096 with shorted inputs.

However, small mismatches in parasitics at the input

can cause this to alter slightly. The offset correction also

results in possible loss of codes at the edges of the full

scale range. With no offset correction, the ADC would clip

in one end before the other, in practice resulting in code

loss at the opposite end. With the output being centered

digitally, the output will clip, and the out of range flags will

be set, before max code is reached. When out of range

flags are set, the code is forced to all ones for over-range

and all zeros for under-range.

Data Format Selection

The output data are presented on offset binary form

when DFRMT is low (connect to OVSS). Setting DFRMT

high (connect to OVDD) results in 2’s complement output

format. Details are shown in Table 1 below.

Table 1: Data Format Description for 2Vpp Full Scale Range

Differential Input Voltage (IP - IN)

Output data: D_9 : D_0

(DFRMT = 0, offset binary)

Output Data: D_9 : D_0

(DFRMT = 1, 2’s complement)

1.0 V

11 1111 1111

01 1111 1111

+0.24mV

10 0000 0000

00 0000 0000

-0.24mV

01 1111 1111

11 1111 1111

-1.0V

00 0000 0000

10 0000 0000

CDK1308 Folha de dados(PDF) 13 Page - Cadeka Microcircuits LLC.

CDK1308 Folha de dados(HTML) 13 Page - Cadeka Microcircuits LLC.

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14

Folha de dados Download

Ligação URL