CDK1304 datasheet(10/11 Pages) CADEKA

10 / 11 page

www.cadeka.com

Data Sheet

Input Protection

All I/O pads are protected with an on-chip protection circuit

shown in Figure 6. This circuit provides ESD robustness

to 3.5kV and prevents latch-up under severe discharge

conditions without degrading analog transition times.

Figure 7. On-Chip Protection Circuit

Power Supply Sequencing Considerations

All logic inputs should be held low until power to the

device has settled to the specific tolerances. Avoid power

decoupling networks with large time constants that could

delay VDD power to the device.

Clock Input

The CDK1304 is driven from a single-ended TTL-input

clock. Because the pipelined architecture operates on the

rising edge of the clock input, the device can operate over

a wide range of input clock duty cycles without degrading

the dynamic performance.

Digital Outputs

The digital outputs (D0–D10) are driven by a separate

supply (OVDD) ranging from +3 V to +5 V. This feature

makes it possible to drive the CDK1304 TTL/CMOS com-

patible outputs with the user’s logic system supply. The

format of the output data (D0–D9) is straight binary. (See

Table 3.) The outputs are latched on the rising edge of

CLK. These outputs can be switched into a tri-state mode

by bringing EN high.

Table 3. Output Data Information

Analog Input

Overrange D10

Output Code D9-D0

+F.S. + 1/2 LSB

1 1 1 1 1 1 1 1 1 1

+F.S. –1/2 LSB

1 1 1 1 1 1 1 1 1Ø

+1/2 F.S.

ØØ ØØØØ ØØØØ

+1/2 LSB

0 0 0 0 0 0 0 0 0 Ø

0.0V

0 0 0 0 0 0 0 0 0 0

(Ø indicates the flickering bit between logic 0 and 1.)

Overrange Output

The Overrange Output (D10) is an indication that the ana-

log input signal has exceeded the positive fullscale input

voltage by 1 LSB. When this condition occurs, D10 will

switch to logic 1. All other data outputs (D0 to D9) will

remain at logic 1 as long as D10 remains at logic 1.

This feature makes it possible to include the CDK1304 in

higher resolution systems.

Evaluation Board

The TBD evaluation board is available to aid designers

in demonstrating the full performance of the CDK1304.

This board includes a reference circuit, clock driver circuit,

output data latches, and an on-board reconstruction of

the digital data. An application note describing the opera-

tion of this board, as well as information on the testing

of the CDK1304, is also available. Contact the factory for

price and availability.

CDK1304 Folha de dados(PDF) 10 Page - Cadeka Microcircuits LLC.

CDK1304 Folha de dados(HTML) 10 Page - Cadeka Microcircuits LLC.

Html Pages

1 2 3 4 5 6 7 8 9 10 11

Folha de dados Download

Ligação URL