FTLX8541E2 datasheet(2/10 Pages) FINISAR

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FTLX8541 Product Specification – November 2007

Page 2

I. Pin Descriptions

Signal Name

Level

I/O

Pin No.

Description

Management and Monitoring Ports

MDIO

Open Drain

I/O

Management Data I/O. Requires

external 10 - 22 kΩ pull-up to the

APS on host.

MDC

1.2 V

CMOS

Management Data Clock Input

PRTAD4

1.2 V

CMOS

Port Address Input bit 4

PRTAD3

1.2 V

CMOS

Port Address Input bit 3

PRTAD2

1.2 V

CMOS

Port Address Input bit 2

PRTAD1

1.2 V

CMOS

Port Address Input bit 1

PRTAD0

1.2 V

CMOS

Port Address Input bit 0

LASI

Open Drain

Link Alarm Status Interrupt Output.

Open Drain Compatible Output with

10 - 20 kΩ pull-up on host.

Logic high = Normal Operation

Logic low = Status Flag Triggered

RESET

Open Drain

Reset Input.

Open Drain Compatible Input with

22 kΩ pull-up to APS internal to

transponder.

Logic high = Normal Operation

Logic low = RESET

Vendor Specific

11,15,16,24

Vendor Specific Pins.

Leave unconnected when not used.

TX ON/OFF

Open Drain

TX ON/OFF Input.

Open Drain Compatible Input with

22 kΩ pull-up to APS internal to

transponder.

Logic high = Transmitter On

Logic low = Transmitter Off

MOD DETECT

Pulled low inside transponder

through a 1 kΩ resistor to Ground

Transmit Functions

Reserved

Reserved For Future Use

TX LANE 3–

TX LANE 3+

Module XAUI Input Lane 3–

Module XAUI Input Lane 3+

TX LANE 2–

TX LANE 2+

Module XAUI Input Lane 2–

Module XAUI Input Lane 2+

TX LANE 1–

TX LANE 1+

Module XAUI Input Lane 1–

Module XAUI Input Lane 1+

TX LANE 0–

TX LANE 0+

AC-coupled,

Internally biased

differential

XAUI

Module XAUI Input Lane 0–

Module XAUI Input Lane 0+

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