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LTC2299

2299fa

2299 F14

OVDD

VDD

0.1

µF

Ω

TYPICAL

DATA

OUTPUT

OGND

OVDD

0.5V

TO 3.6V

PREDRIVER

LOGIC

DATA

FROM

LATCH

LTC2299

Digital Output Buffers

Figure 14 shows an equivalent circuit for a single output

buffer. Each buffer is powered by OVDD and OGND, iso-

lated from the ADC power and ground. The additional

N-channel transistor in the output driver allows operation

down to low voltages. The internal resistor in series with

the output makes the output appear as 50

Ω to external

circuitry and may eliminate the need for external damping

resistors.

Maximum and Minimum Conversion Rates

The maximum conversion rate for the LTC2299 is 80Msps.

For the ADC to operate properly, the CLK signal should

have a 50% (

±5%) duty cycle. Each half cycle must have

at least 5.9ns for the ADC internal circuitry to have enough

settling time for proper operation.

An optional clock duty cycle stabilizer circuit can be used

if the input clock has a non 50% duty cycle. This circuit

uses the rising edge of the CLK pin to sample the analog

input. The falling edge of CLK is ignored and the internal

falling edge is generated by a phase-locked loop. The

input clock duty cycle can vary from 40% to 60% and the

clock duty cycle stabilizer will maintain a constant 50%

internal duty cycle. If the clock is turned off for a long

period of time, the duty cycle stabilizer circuit will require

a hundred clock cycles for the PLL to lock onto the input

clock. To use the clock duty cycle stabilizer, the MODE pin

should be connected to 1/3VDD or 2/3VDD using external

resistors. The MODE pin controls both Channel A and

Channel B—the duty cycle stabilizer is either on or off for

both channels.

The lower limit of the LTC2299 sample rate is determined

by droop of the sample-and-hold circuits. The pipelined

architecture of this ADC relies on storing analog signals on

small valued capacitors. Junction leakage will discharge

the capacitors. The specified minimum operating fre-

quency for the LTC2299 is 1Msps.

DIGITAL OUTPUTS

Table 1 shows the relationship between the analog input

voltage, the digital data bits, and the overflow bit.

Table 1. Output Codes vs Input Voltage

AIN+ – AIN–

D13 – D0

(2V RANGE)

(OFFSET BINARY)

(2’s COMPLEMENT)

>+1.000000V

11 1111 1111 1111

01 1111 1111 1111

+0.999878V

11 1111 1111 1111

01 1111 1111 1111

+0.999756V

11 1111 1111 1110

01 1111 1111 1110

+0.000122V

10 0000 0000 0001

00 0000 0000 0001

0.000000V

10 0000 0000 0000

00 0000 0000 0000

–0.000122V

01 1111 1111 1111

11 1111 1111 1111

–0.000244V

01 1111 1111 1110

11 1111 1111 1110

–0.999878V

00 0000 0000 0001

10 0000 0000 0001

–1.000000V

00 0000 0000 0000

10 0000 0000 0000

<–1.000000V

00 0000 0000 0000

10 0000 0000 0000

Figure 14. Digital Output Buffer

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