AX2000-1CSG896 datasheet(55/226 Pages) ACTEL

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Axcelerator Family FPGAs

v2.7

2-41

LVPECL

Low-Voltage Positive Emitter-Coupled Logic (LVPECL) is another differential I/O standard. It requires that one data bit

is carried through two signal lines. Like LVDS, two pins are needed. It also requires external resistor termination. The

voltage swing between these two signal lines is approximately 850 mV.

The LVPECL circuit is similar to the LVDS scheme. It requires four external resistors, three for the driver and one for the

receiver. The values for the three driver resistors are different from that of LVDS since the output voltage levels are

different. Please note that the VOH levels are 200 mV below the standard LVPECL levels.

Figure 2-26 • LVPECL Board-Level Implementation

Table 2-58 • DC Input and Output Levels

DC Parameter

Min.

Typ.

Max.

Units

Min.

Max.

Min.

Max.

Min.

Max.

VCCI

33.3

3.6

VOH

1.8

2.11

1.92

2.28

2.13

2.41

VOL

0.96

1.27

1.06

1.43

1.3

1.57

VIH

1.49

2.72

1.49

2.72

1.49

2.72

VIL

0.86

2.125

0.86

2.125

0.86

2.125

Differential Input Voltage

0.3

Table 2-59 • AC Waveforms, Measuring Points, and Capacitive Loads

Input Low (V)

Input High (V)

Measuring Point* (V)

1.6-0.3

1.6+0.3

1.6

* Measuring Point = Vtrip

187

100

ZO=50

100

–

INBUF_LVPECL

OUTBUF_LVPECL

FPGA

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