MPC8313CVRAFDB datasheet(40/100 Pages) FREESCALE

40 / 100 page

MPC8313E PowerQUICC™ II Pro Processor Hardware Specifications, Rev. 2.1

Freescale Semiconductor

High-Speed Serial Interfaces (HSSI)

or AC coupled into the unused phase (SD_REF_CLK) through the same source impedance as

the clock input (SD_REF_CLK) in use.

Figure 24. Differential Reference Clock Input DC Requirements (External DC-Coupled)

Figure 25. Differential Reference Clock Input DC Requirements (External AC-Coupled)

Figure 26. Single-Ended Reference Clock Input DC Requirements

9.2.3

Interfacing With Other Differential Signaling Levels

•

With on-chip termination to XCOREVSS, the differential reference clocks inputs are HCSL

(high-speed current steering logic) compatible DC coupled.

•

Many other low voltage differential type outputs like LVDS (low voltage differential signaling) can

be used but may need to be AC coupled due to the limited common mode input range allowed (100

to 400 mV) for DC-coupled connection.

•

LVPECL outputs can produce a signal with too large of an amplitude and may need to be

DC-biased at the clock driver output first, then followed with series attenuation resistor to reduce

the amplitude, in addition to AC coupling.

SD_REF_CLK

Vmax < 800 mV

Vmin > 0 V

100 mV < Vcm < 400 mV

200 mV < Input Amplitude or Differential Peak < 800 mV

SD_REF_CLK

Vcm

200 mV < Input Amplitude or Differential Peak < 800 mV

Vmax < Vcm + 400 mV

Vmin > Vcm – 400 mV

SD_REF_CLK

400 mV < SD_REF_CLK Input Amplitude < 800 mV

MPC8313CVRAFDB Folha de dados(PDF) 40 Page - Freescale Semiconductor, Inc