TSA1201 datasheet(12/20 Pages) STMICROELECTRONICS

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TSA1201 APPLICATION NOTE

DETAILED INFORMATION

The TSA1201 is a High Speed analog to digital

converter based on a pipeline architecture and the

latest deep submicron CMOS process to achieve

the best performances in terms of linearity and

power consumption.

The pipeline structure consists of 11 internal

conversion stages in which the analog signal is

fed and sequencially converted into digital data.

Each 10 first stages consists of an Analog to

Digital converter, a Digital to Analog converter, a

Sample and Hold and a gain of 2 amplifier. A

1.5-bit conversion resolution is achieved in each

stage. The latest stage simply is a comparator.

Each resulting LSB-MSB couple is then time

shifted to recover from the delay caused by

conversion. Digital data correction completes the

processing by recovering from the redundancy of

the (LSB-MSB) couple for each stage. The

corrected data are outputed through the digital

buffers.

Signal input is sampled on the rising edge of the

clock while digital outputs are delivered on the

falling edge of the clock.

The advantages of such a converter reside in the

combination of pipeline architecture and the most

advanced technologies. The highest dynamic

performances are achieved while consumption

remains at the lowest level.

Some functionalites have been added in order to

simplify as much as possible the application

board. These operational modes are described in

the following table.

The TSA1201 is pin to pin compatible with the

8bits/40Msps

TSA0801,

the

10bits/25Msps

TSA1001 and the 10bits/50Msps TSA1002. This

ensures a conformity with the product family and

above all, an easy upgrade of the application

OPERATIONAL MODES DESCRIPTION

Data Format Select (DFSB)

When set to low level (VIL), the digital input DFSB

provides a two’s complement digital output MSB.

This can be of interest when performing some

further signal processing.

When set to high level (VIH), DFSB provides a

standard binary output coding.

Output Enable (OEB)

When set to low level (VIL), all digital outputs

remain active and are in low impedance state.

When set to high level (VIH), all digital outputs

buffers are in high impedance state while the

converter goes on sampling. When OEB is set to a

low level again, the data are then present on the

output with a very short Ton delay.

Therefore, this allows the chip select of the device.

The timing diagram summarizes this functionality.

Inputs

Outputs

Analog input differential level

DFSB OEB

SRC

Most Significant Bit (MSB)

(VIN-VINB)

RANGE

CLK

D11

-RANGE

(VIN-VINB)

CLK

D11

RANGE> (VIN-VINB) >-RANGE

CLK

D11

(VIN-VINB)

RANGE

CLK

D11 Complemented

-RANGE

(VIN-VINB)

CLK

D11 Complemented

RANGE> (VIN-VINB) >-RANGE

CLK

D11 Complemented

CLK

25Msps compliant slew rate

CLK

50Msps compliant slew rate

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