TS68230FN datasheet(32/61 Pages) STMICROELECTRONICS

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cles. Typically, a four clock cycle pulse is ge-

nerated. But in the case that a subsequent H1

asserted edge occurs before termination of the

pulse, H2 is negated asynchronously. Thus,

anytime after the leading edge of the H2 pulse,

new data may be transferred to the double-

buffered output latches. The H2S status bit is

always clear. When H12 enable is clear, H2 is

held negated.

The DMAREQ pin may be associated with either in-

put transfers (H3) or output transfers (H1), but not

both. Refer to table 3.4 for a summary of the port B

data register responses in mode 2.

Programmable Options Mode 2 - Port A Submode XX and Port B Submode XX

Table 3.4 : Mode 2 Port B Data Paths.

Mode

Read Port B Data Register

Write Port B Data Register

FIL, D. B.

IOL/FOL, D. B.

Abbreviations :

IOL - Initial Output Latch

FOL - Final Output Latch

FIL - Final Input Latch

D. B. - Double Buffered

PACR

7 6

Port A Submode

X X

Submode XX.

PACR

5 4 3

H2 Control

X X 0

Output pin - interlocked output handshake protocol, H2S is always cleared.

X X 1

Output pin - pulsed output handshake protocol, H2S is always cleared.

PACR

H2 Interrupt Enable

The H2 interrupt is disabled.

The H2 interrupt is enabled.

PACR

H1 SVCRQ Enable

The H1 interrupt and DMA request are disabled.

The H1 interrupt and DMA request are enabled.

PACR

H1 Status Control

The H1 status bit is set when either the port B initial or final output latch can accept new data. It

is clear when both latches are full and cannot accept new data.

The H1S status bit is set when both of the port B output latches are empty. It is clear when at

least one latch is full.

PBCR

7 6

Port B Submode

X X

Submode XX.

TS68230

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