TDA9110 datasheet(17/29 Pages) STMICROELECTRONICS

17 / 29 page

Loop

Filter

1.6V

6.4V

1.6V

0 0.875T

FLIP FLOP

(1.3V < V

< 6V)

4I0

Figure 10 : Details of VCO

LOCKDET

H-LOCKCAP

COMP1

INPUT

INTERFACE

HSYNC

High

CHARGE

PUMP

Low

PLL

INHIBITION

VCO

PLL1F

PHASE

ADJUST

I2C

HPOS

Adj.

OSC

TRAMEXT

LOCK/UNLOCK

STATUS

Figure 9 : Principle Diagram

OPERATING DESCRIPTION (continued)

The control voltage of the VCO is between 1.33V

and 6V (see Figure 10). The theorical frequency

range of this VCO is in the ratio of 1 to 4.5. The

effective frequency range has to be smaller (1 to

4.2) due to clamp intervention on filter lowest value.

In order to increase this effective frequency range,

to a possiblerange of 1 to6.0 one can add a resistor

from Pin 6 to Href leading.

The synchro frequency must always be higher than

the free running frequency. For example, when

using a synchro range between 31kHz and 96kHz,

the suggested free running frequency is 25kHz.

The PLL1 ensures the coincidence between the

leading edge of the synchro signal and a phase

reference obtained by comparison between the

sawtooth of the VCO and an internal DC voltage

which is I

2C adjustable between 2.65V and 3.75V

(corresponding to

± 10%) (see Figure 11).

H Osc

Sawtooth

Phase REF1

H Synchro

1.6V

6.4V

2.60V<Vb<3.80V

7/8T

1/8T

Phase REF1 is obtained by comparison between the sawtooth and

a DC voltage adjustable between 2.60V and 3.80V. The PLL1

ensures the exact coincidence between the signals phase REF

and HSYNS. A

± T/10 phase adjustment is possible.

Figure 11 : PLL1 Timing Diagram

TDA9110

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