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TDA7580 Folha de dados(PDF) 18 Page - STMicroelectronics |
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TDA7580 Folha de dados(HTML) 18 Page - STMicroelectronics |
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18 / 31 page ![]() TDA7580 18/31 SPI INTERFACE Figure 8. SPI Timings Symbol Description Value Unit TDSP Internal DSP Clock Period (Typical 1/74.1MHz) 13.495 ns MASTER tsclk Minimum Clock Cycle 12*TDSP ns tdtr Minimum Sclk edge to MOSI valid 40 ns tsetup Minimum MISO setup time 16 ns thold Minimum MISO hold time 9 ns tsclkh Minimum SCK high time 0.5*tsclk ns tsclkl Minimum SCK low time 0.5*tsclk ns tsssetup Minimum SS setup time 40 ns tsshold Minimum SS hold time 25 ns SLAVE tsclk Minimum Clock Cycle 12*TDSP ns tdtr Minimum Sclk edge to MOSI valid 40 ns tsetup Minimum MOSI setup time 16 ns thold Minimum MOSI hold time 9 ns tsclkh Minimum SCK high time 0.5*tsclk ns tsclk tsclkl tdtr tsssetup tsetup tsclkh thold tsshold Valid MISO SS SCL Valid (CPOL=0,CPHA=0) MOSI |
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