7906 datasheet(91/531 Pages) RENESAS

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7906 Group User’s Manual Rev.2.0

INTERRUPTS

6-12

6.6 Interrupt priority level detection time

When the interrupt priority level detection time has passed after sampling starts, an interrupt request is

accepted. The interrupt priority level detection time can be selected by software. (See Figure 6.6.1.) Usually,

select “2 cycles of fsys” as the interrupt priority level detection time.

Figure 6.6.2 shows the interrupt priority level detection time.

6.6 Interrupt priority level detection time

Fig. 6.6.2 Interrupt priority level detection time

fsys

Op-code fetch cycle

Sampling pulse

(a) 7 cycles of fsys

(b) 4 cycles of fsys

Interrupt priority level

detection time

(Note)

Note: The pulse resides when “2 cycles of fsys” is selected.

Fig. 6.6.1 Structure of processor mode register 0

Bit name

Bit

Processor mode register 0 (Address 5E16)

Function

At reset

R/W

Processor mode bits

Interrupt priority detection time

select bits

Software reset bit

Fix this bit to “0.”

b7 b6 b5 b4 b3 b2 b1 b0

0 0 : Single-chip mode

0 1 : Do not select.

1 0 : Do not select.

1 1 : Do not select.

b1 b0

0 0 : 7 cycles of fsys

0 1 : 4 cycles of fsys

1 0 : 2 cycles of fsys

1 1 : Do not select.

b5 b4

The microcomputer is reset by writing “1” to this

bit. The value is “0” at reading.

0X X 0 0

Any of these bits may be either “0” or “1.”

X : It may be either “0” or “1.”

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