7733 datasheet(241/940 Pages) RENESAS

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SERIAL I/O

7733 Group User’s Manual

8–38

8.3 Clock synchronous serial I/O mode

[When not using interrupts]

[When using interrupts]

A UARTi receive interrupt request occurs

when reception is completed.

UARTi receive interrupt

This diagram indicates bits and registers

required for processing.

Refer to Figure 8.3.15 for details about the

change of flag status and the occurrence timing

of an interrupt request.

Processing after reading out receive data

UART0 receive buffer register (address 36 16)

UART1 receive buffer register (address 3E 16)

UART2 receive buffer register (address 6A 16)

Reading of the receive data

Receive data is read out.

UART0 transmit/receive control register 1 (address 35 16)

UART1 transmit/receive control register 1 (address 3D 16)

UART2 transmit/receive control register 1 (address 69 16)

Receive completion flag

0: Reception is not completed.

1: Reception is completed.

Checking the completion of reception

UART0 transmit/receive control register 1 (address 35 16)

UART1 transmit/receive control register 1 (address 3D 16)

UART2 transmit/receive control register 1 (address 69 16)

Checking the error

Overrun error flag

0: No overrun error is detected.

1: Error is detected.

Fig. 8.3.12 Processing after reception is completed

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