7733 datasheet(240/940 Pages) RENESAS

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SERIAL I/O

7733 Group User’s Manual

8–37

8.3 Clock synchronous serial I/O mode

Port P8 direction register (address 14 16)

RXD0 pin

RXD1 pin

Continued from

“Initial setting example for related registers when receiving (1)”

on the proceeding page

UART0 receive interrupt control register (address 72 16)

UART1 receive interrupt control register (address 74 16)

A-D/UART2 trans./rece. interrupt control register (address 70 16)

Interrupt priority level selection bits

When using interrupts, one of level 1 to 7 must be set.

When disabling interrupts, level 0 must be set.

UART0 transmission buffer register (address 32 16)

UART1 transmission buffer register (address 3A 16)

UART2 transmission buffer register (address 66 16)

Dummy data is set.

UART0 transmit/receive control register 1(address 35 16)

UART1 transmit/receive control register 1(address 3D 16)

UART2 transmit/receive control register 1(address 69 16)

Transmit enable bit ( Note 2)

1: Transmission is enabled.

Receive enable bit ( Note 2)

1: Receptipn is enabled.

Reception is started.

Notes 2: Set the receive enable bit and the transmit

enable bit to “1” simultaneously.

Port P7 direction register (address 11 16)

RXD2 pin (Note 1)

Notes 1: In the 7733 Group or the 7735 Group, set this bit.

In the 7736 Group, it is not necessary to set this bit.

Fig. 8.3.11 Initial setting example for related registers when receiving (2)

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