H8SLASH3003 datasheet(79/715 Pages) RENESAS

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Bits 6 to 4—Standby Timer Select (STS2 to STS0): These bits select the length of time the CPU

and on-chip supporting modules wait for the internal clock oscillator to settle when software

standby mode is exited by an external interrupt. Set these bits so that the waiting time will be at

least 8 ms at the system clock rate. For further information about waiting time selection, see

section 17.4.3, Selection of Oscillator Waiting Time after Exit from Software Standby Mode.

Bit 6

Bit 5

Bit 4

STS2

STS1

STS0

Description

000Waiting time = 8192 states

(Initial value)

001Waiting time = 16384 states

010Waiting time = 32768 states

011Waiting time = 65536 states

—

Waiting time = 131072 states

—

Waiting time = 4 states

Bit 3—User Bit Enable (UE): Selects whether to use the UI bit in the condition code register as a

user bit or an interrupt mask bit.

Bit 3

Description

UI bit in CCR is used as an interrupt mask bit

UI bit in CCR is used as a user bit

(Initial value)

Bit 2—NMI Edge Select (NMIEG): Selects the valid edge of the NMI input.

Bit 2

NMIEG

Description

An interrupt is requested at the falling edge of NMI

(Initial value)

An interrupt is requested at the rising edge of NMI

Bit 1—Reserved: Read-only bit, always read as 1.

Bit 0—RAM Enable (RAME): Enables or disables the on-chip RAM. The RAME bit is

initialized by the rising edge of the RES signal. It is not initialized in software standby mode.

Bit 0

RAME

Description

On-chip RAM is disabled

On-chip RAM is enabled

(Initial value)

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