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2.2 Interrupts

APPLICATION

2–25

3822 GROUP USER’S MANUAL

(3) Interrupt control register 1 (ICON1) and interrupt control register 2 (ICON2)

The interrupt control register 1 (address 003E16) and the interrupt control register 2 (address 003F16)

control each interrupt request source.

Figure 2.2.11 shows the structure of the interrupt control register 1 and Figure 2.2.12 shows the

structure of the interrupt control register 2.

When an interrupt enable bit is “0,” the corresponding interrupt request is disabled. If an interrupt

request occurs when this bit is “0,” the corresponding interrupt request bit is only set to “1,” and the

interrupt request is not accepted.

When an interrupt enable bit is “1,” the corresponding interrupt request is enabled. If an interrupt

request occurs when this bit is “1,” the interrupt request is accepted (at interrupt disable flag = “0”).

Each interrupt enable bit can be set to “0” or “1” by software.

Fig. 2.2.11 Structure of interrupt control register 1

b7 b6 b5 b4 b3 b2 b1 b0

Interrupt control register 1 (ICON1) [Address 3E16]

Name

Functions

At reset RW

Interrupt control register 1

INT0 interrupt enable

bit

0 : Interrupts disabled

1 : Interrupts enabled

INT1 interrupt enable

bit

Serial I/O receive

interrupt enable bit

Serial I/O transmit

interrupt enable bit

Timer X interrupt

enable bit

Timer Y interrupt

enable bit

Timer 2 interrupt

enable bit

Timer 3 interrupt

enable bit

0 : Interrupts disabled

1 : Interrupts enabled

0 : Interrupts disabled

1 : Interrupts enabled

0 : Interrupts disabled

1 : Interrupts enabled

0 : Interrupts disabled

1 : Interrupts enabled

0 : Interrupts disabled

1 : Interrupts enabled

0 : Interrupts disabled

1 : Interrupts enabled

0 : Interrupts disabled

1 : Interrupts enabled

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